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| author | Cédric Le Goater <clg@kaod.org> | 2019-01-17 08:53:24 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-02-04 18:44:18 +1100 |
| commit | 40a5056c4130efc60ab0639e93d6d0c509326e8a (patch) | |
| tree | 309997620c372aeca337d2170508b4010512b432 /hw/intc | |
| parent | d8e81d6e6093738c23b457b607c44a75a6952dc8 (diff) | |
| download | qemu-40a5056c4130efc60ab0639e93d6d0c509326e8a.zip qemu-40a5056c4130efc60ab0639e93d6d0c509326e8a.tar.gz qemu-40a5056c4130efc60ab0639e93d6d0c509326e8a.tar.bz2 | |
xive: add a get_tctx() method to the XiveRouter
It provides a mean to retrieve the XiveTCTX of a CPU. This will become
necessary with future changes which move the interrupt presenter
object pointers under the PowerPCCPU machine_data.
The PowerNV machine has an extra requirement on TIMA accesses that
this new method addresses. The machine can perform indirect loads and
stores on the TIMA on behalf of another CPU. The PIR being defined in
the controller registers, we need a way to peek in the controller
model to find the PIR value.
The XiveTCTX is moved above the XiveRouter definition to avoid forward
typedef declarations.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/spapr_xive.c | 8 | ||||
| -rw-r--r-- | hw/intc/xive.c | 16 |
2 files changed, 18 insertions, 6 deletions
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index d391177..136d872 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -390,6 +390,13 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, g_assert_not_reached(); } +static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + + return cpu->tctx; +} + static const VMStateDescription vmstate_spapr_xive_end = { .name = TYPE_SPAPR_XIVE "/end", .version_id = 1, @@ -454,6 +461,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data) xrc->write_end = spapr_xive_write_end; xrc->get_nvt = spapr_xive_get_nvt; xrc->write_nvt = spapr_xive_write_nvt; + xrc->get_tctx = spapr_xive_get_tctx; } static const TypeInfo spapr_xive_info = { diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 7f567a5..2e9b8ef 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -320,8 +320,7 @@ static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) static void xive_tm_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - PowerPCCPU *cpu = POWERPC_CPU(current_cpu); - XiveTCTX *tctx = cpu->tctx; + XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu); const XiveTmOp *xto; /* @@ -359,8 +358,7 @@ static void xive_tm_write(void *opaque, hwaddr offset, static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) { - PowerPCCPU *cpu = POWERPC_CPU(current_cpu); - XiveTCTX *tctx = cpu->tctx; + XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu); const XiveTmOp *xto; /* @@ -1107,6 +1105,13 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); } +XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs) +{ + XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); + + return xrc->get_tctx(xrtr, cs); +} + /* * The thread context register words are in big-endian format. */ @@ -1182,8 +1187,7 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, */ CPU_FOREACH(cs) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - XiveTCTX *tctx = cpu->tctx; + XiveTCTX *tctx = xive_router_get_tctx(xrtr, cs); int ring; /* |