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| author | Keqian Zhu <zhukeqian1@huawei.com> | 2020-04-13 17:15:50 +0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-04-30 11:52:27 +0100 |
| commit | 1e11a139bfed55cb2de7b2eaa1e53f3cf6180d13 (patch) | |
| tree | caaef51feccae5cff63e30edfb5e3372cce83766 /hw/intc | |
| parent | c8aeef3aed6beef14175f9c6744b2ea30fc309d9 (diff) | |
| download | qemu-1e11a139bfed55cb2de7b2eaa1e53f3cf6180d13.zip qemu-1e11a139bfed55cb2de7b2eaa1e53f3cf6180d13.tar.gz qemu-1e11a139bfed55cb2de7b2eaa1e53f3cf6180d13.tar.bz2 | |
bugfix: Use gicr_typer in arm_gicv3_icc_reset
The KVM_VGIC_ATTR macro expect the second parameter as gicr_typer,
of which high 32bit is constructed by mp_affinity. For most case,
the high 32bit of mp_affinity is zero, so it will always access the
ICC_CTLR_EL1 of CPU0.
Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
Message-id: 20200413091552.62748-2-zhukeqian1@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/arm_gicv3_kvm.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 49304ca..ca43bf8 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -658,13 +658,11 @@ static void kvm_arm_gicv3_get(GICv3State *s) static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu; GICv3State *s; GICv3CPUState *c; c = (GICv3CPUState *)env->gicv3state; s = c->gic; - cpu = ARM_CPU(c->cpu); c->icc_pmr_el1 = 0; c->icc_bpr[GICV3_G0] = GIC_MIN_BPR; @@ -681,7 +679,7 @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) /* Initialize to actual HW supported configuration */ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, - KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity), + KVM_VGIC_ATTR(ICC_CTLR_EL1, c->gicr_typer), &c->icc_ctlr_el1[GICV3_NS], false, &error_abort); c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; |