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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-01-07 17:07:59 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-01-07 17:07:59 +0000 |
| commit | e07f844599525685db44ce74bf4ab12025d1d96a (patch) | |
| tree | c7b3f49b5bf211f0e38ec01210a2d34748f897dd /hw/intc/gicv3_internal.h | |
| parent | b87fab1c8e8977e8ea1233bafdbfa37090eefabf (diff) | |
| download | qemu-e07f844599525685db44ce74bf4ab12025d1d96a.zip qemu-e07f844599525685db44ce74bf4ab12025d1d96a.tar.gz qemu-e07f844599525685db44ce74bf4ab12025d1d96a.tar.bz2 | |
hw/intc/arm_gicv3_its: Use FIELD macros for DTEs
Currently the ITS code that reads and writes DTEs uses open-coded
shift-and-mask to assemble the various fields into the 64-bit DTE
word. The names of the macros used for mask and shift values are
also somewhat inconsistent, and don't follow our usual convention
that a MASK macro should specify the bits in their place in the word.
Replace all these with use of the FIELD macro.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw/intc/gicv3_internal.h')
| -rw-r--r-- | hw/intc/gicv3_internal.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 5a63e9e..6a3b145 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -393,9 +393,10 @@ FIELD(ITE_H, VPEID, 16, 16) * Valid = 1 bit,ITTAddr = 44 bits,Size = 5 bits */ #define GITS_DTE_SIZE (0x8ULL) -#define GITS_DTE_ITTADDR_SHIFT 6 -#define GITS_DTE_ITTADDR_MASK MAKE_64BIT_MASK(GITS_DTE_ITTADDR_SHIFT, \ - ITTADDR_LENGTH) + +FIELD(DTE, VALID, 0, 1) +FIELD(DTE, SIZE, 1, 5) +FIELD(DTE, ITTADDR, 6, 44) /* * 8 bytes Collection Table Entry size |