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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-01-22 18:24:36 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-01-28 14:29:47 +0000 |
| commit | 703090770c19dad32f42a8bc27393ed01b7bc42f (patch) | |
| tree | 13018a63c85eb9a93338dc2dd19beb1a63285acb /hw/intc/gicv3_internal.h | |
| parent | 0cc38f359cbb50dd4f182b4ad3b7f7a17b1a4721 (diff) | |
| download | qemu-703090770c19dad32f42a8bc27393ed01b7bc42f.zip qemu-703090770c19dad32f42a8bc27393ed01b7bc42f.tar.gz qemu-703090770c19dad32f42a8bc27393ed01b7bc42f.tar.bz2 | |
hw/intc/arm_gicv3: Honour GICD_CTLR.EnableGrp1NS for LPIs
The GICD_CTLR distributor register has enable bits which control
whether the different interrupt groups (Group 0, Non-secure Group 1
and Secure Group 1) are forwarded to the CPU. We get this right for
traditional interrupts, but forgot to account for it when adding
LPIs. LPIs are always Group 1 NS and if the EnableGrp1NS bit is not
set we must not forward them to the CPU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-7-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/gicv3_internal.h')
0 files changed, 0 insertions, 0 deletions