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authorPhilippe Mathieu-Daudé <philmd@redhat.com>2019-10-10 15:15:23 +0200
committerEduardo Habkost <ehabkost@redhat.com>2019-10-15 18:18:08 -0300
commitd96c81f9b8bdeb19417a54178759ac170f080cb2 (patch)
tree82fe16428bab3b5708f128b225faaee5a6668316 /hw/ide
parentee358e919e385fdc79d59d0d47b4a81e349cd5c9 (diff)
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hw/ide/sii3112: Convert reset handler to DeviceReset
The SiI3112A SATA controller is a PCI device, it will be reset when the PCI bus it stands on is reset. Convert its reset handler into a proper Device reset method. Reviewed-by: Li Qiang <liq3ea@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191010131527.32513-5-philmd@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'hw/ide')
-rw-r--r--hw/ide/sii3112.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c
index 2181260..06605d7 100644
--- a/hw/ide/sii3112.c
+++ b/hw/ide/sii3112.c
@@ -15,7 +15,6 @@
#include "qemu/osdep.h"
#include "hw/ide/pci.h"
#include "qemu/module.h"
-#include "sysemu/reset.h"
#include "trace.h"
#define TYPE_SII3112_PCI "sii3112"
@@ -237,9 +236,9 @@ static void sii3112_set_irq(void *opaque, int channel, int level)
sii3112_update_irq(s);
}
-static void sii3112_reset(void *opaque)
+static void sii3112_reset(DeviceState *dev)
{
- SiI3112PCIState *s = opaque;
+ SiI3112PCIState *s = SII3112_PCI(dev);
int i;
for (i = 0; i < 2; i++) {
@@ -290,7 +289,6 @@ static void sii3112_pci_realize(PCIDevice *dev, Error **errp)
s->bmdma[i].bus = &s->bus[i];
ide_register_restart_cb(&s->bus[i]);
}
- qemu_register_reset(sii3112_reset, s);
}
static void sii3112_pci_class_init(ObjectClass *klass, void *data)
@@ -303,6 +301,7 @@ static void sii3112_pci_class_init(ObjectClass *klass, void *data)
pd->class_id = PCI_CLASS_STORAGE_RAID;
pd->revision = 1;
pd->realize = sii3112_pci_realize;
+ dc->reset = sii3112_reset;
dc->desc = "SiI3112A SATA controller";
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}