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authorGerd Hoffmann <kraxel@redhat.com>2009-08-20 15:22:22 +0200
committerAnthony Liguori <aliguori@us.ibm.com>2009-08-27 20:43:33 -0500
commit3d2bf4a1093a8598a5ac6038a2510ef864a68118 (patch)
treede18c26a89c4470d1e9e111a425604bbdb1f4b2b /hw/ide.c
parentb884220990ef19d55fc07cebea910d1745b203d3 (diff)
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ide: split away ide-mmio.c
create ide-mmio.c and place mmio support there. only build ide-mmio support for platforms using it. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'hw/ide.c')
-rw-r--r--hw/ide.c92
1 files changed, 0 insertions, 92 deletions
diff --git a/hw/ide.c b/hw/ide.c
index 4a12ea8..7e4e83b0 100644
--- a/hw/ide.c
+++ b/hw/ide.c
@@ -2700,98 +2700,6 @@ void ide_dma_cancel(BMDMAState *bm)
}
/***********************************************************/
-/* MMIO based ide port
- * This emulates IDE device connected directly to the CPU bus without
- * dedicated ide controller, which is often seen on embedded boards.
- */
-
-typedef struct {
- IDEBus *bus;
- int shift;
-} MMIOState;
-
-static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr)
-{
- MMIOState *s = (MMIOState*)opaque;
- IDEBus *bus = s->bus;
- addr >>= s->shift;
- if (addr & 7)
- return ide_ioport_read(bus, addr);
- else
- return ide_data_readw(bus, 0);
-}
-
-static void mmio_ide_write (void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- MMIOState *s = (MMIOState*)opaque;
- IDEBus *bus = s->bus;
- addr >>= s->shift;
- if (addr & 7)
- ide_ioport_write(bus, addr, val);
- else
- ide_data_writew(bus, 0, val);
-}
-
-static CPUReadMemoryFunc * const mmio_ide_reads[] = {
- mmio_ide_read,
- mmio_ide_read,
- mmio_ide_read,
-};
-
-static CPUWriteMemoryFunc * const mmio_ide_writes[] = {
- mmio_ide_write,
- mmio_ide_write,
- mmio_ide_write,
-};
-
-static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr)
-{
- MMIOState *s= (MMIOState*)opaque;
- IDEBus *bus = s->bus;
- return ide_status_read(bus, 0);
-}
-
-static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- MMIOState *s = (MMIOState*)opaque;
- IDEBus *bus = s->bus;
- ide_cmd_write(bus, 0, val);
-}
-
-static CPUReadMemoryFunc * const mmio_ide_status[] = {
- mmio_ide_status_read,
- mmio_ide_status_read,
- mmio_ide_status_read,
-};
-
-static CPUWriteMemoryFunc * const mmio_ide_cmd[] = {
- mmio_ide_cmd_write,
- mmio_ide_cmd_write,
- mmio_ide_cmd_write,
-};
-
-void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
- qemu_irq irq, int shift,
- BlockDriverState *hd0, BlockDriverState *hd1)
-{
- MMIOState *s = qemu_mallocz(sizeof(MMIOState));
- IDEBus *bus = qemu_mallocz(sizeof(*bus));
- int mem1, mem2;
-
- ide_init2(bus, hd0, hd1, irq);
-
- s->bus = bus;
- s->shift = shift;
-
- mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s);
- mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s);
- cpu_register_physical_memory(membase, 16 << shift, mem1);
- cpu_register_physical_memory(membase2, 2 << shift, mem2);
-}
-
-/***********************************************************/
/* CF-ATA Microdrive */
#define METADATA_SIZE 0x20