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| author | Paolo Bonzini <pbonzini@redhat.com> | 2024-07-03 11:29:17 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2024-07-03 18:41:26 +0200 |
| commit | 29a51b2bb55c6b2e0224d82c154d82498ccece35 (patch) | |
| tree | b46c7d6dd6d8a309479a16510ffc61df81d5acc0 /hw/i386 | |
| parent | 9b40d376f66640eb7b6080ca000c866dfe630dc7 (diff) | |
| download | qemu-29a51b2bb55c6b2e0224d82c154d82498ccece35.zip qemu-29a51b2bb55c6b2e0224d82c154d82498ccece35.tar.gz qemu-29a51b2bb55c6b2e0224d82c154d82498ccece35.tar.bz2 | |
target/i386: do not include undefined bits in the AMD topoext leaf
Commit d7c72735f61 ("target/i386: Add new EPYC CPU versions with updated
cache_info", 2023-05-08) ensured that AMD-defined CPU models did not
have the 'complex_indexing' bit set, but left it set in "-cpu host"
which uses the default ("legacy") cache information.
Reimplement that commit using a CPU feature, so that it can be applied
to all guests using a new machine type, independent of the CPU model.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw/i386')
| -rw-r--r-- | hw/i386/pc.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 7741506..5dff914 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -80,6 +80,7 @@ { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, GlobalProperty pc_compat_9_0[] = { + { TYPE_X86_CPU, "x-amd-topoext-features-only", "false" }, { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" }, { TYPE_X86_CPU, "guest-phys-bits", "0" }, { "sev-guest", "legacy-vm-type", "true" }, |