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| author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2013-12-03 21:57:59 -0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-12-10 13:28:50 +0000 |
| commit | a03f742983f9b6ed03913b30005b6f053290d285 (patch) | |
| tree | d15a4ba905efa362779c69fe9cfe5ecb03bd660f /hw/i2c | |
| parent | 63af1e0cff8879a3ddd1b08abb3172b49fb88c88 (diff) | |
| download | qemu-a03f742983f9b6ed03913b30005b6f053290d285.zip qemu-a03f742983f9b6ed03913b30005b6f053290d285.tar.gz qemu-a03f742983f9b6ed03913b30005b6f053290d285.tar.bz2 | |
net/cadence_gem: Implement SAR match bit in rx desc
Bit 27 of the RX buffer desc word 1 should be set when the packet was
accepted due to specific address register match. Implement.
This feature is absent from the Xilinx documentation (UG585) but the
behaviour is tested as accurate on real hardware.
Reported-by: Deepika Dhamija <deepika@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 7e3f26fc4ab244e8123efc12723e7164730abdcb.1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/i2c')
0 files changed, 0 insertions, 0 deletions