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| author | Peter Maydell <peter.maydell@linaro.org> | 2018-08-20 11:24:33 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-08-20 11:24:33 +0100 |
| commit | 156448ab640baaeca185787eb303fe4d63edca26 (patch) | |
| tree | ffcfdd37ce22d96062f5e83c7f449d2cec6af97c /hw/dma | |
| parent | c193304d4f9ef21c51ff412f6279ad459eedd438 (diff) | |
| download | qemu-156448ab640baaeca185787eb303fe4d63edca26.zip qemu-156448ab640baaeca185787eb303fe4d63edca26.tar.gz qemu-156448ab640baaeca185787eb303fe4d63edca26.tar.bz2 | |
hw/dma/pl080: Correct bug in register address decode logic
A bug in the handling of the register address decode logic
for the PL08x meant that we were incorrectly treating
accesses to the DMA channel registers (DMACCxSrcAddr,
DMACCxDestaddr, DMACCxLLI, DMACCxControl, DMACCxConfiguration)
as bad offsets. Fix this long-standing bug.
Fixes: https://bugs.launchpad.net/qemu/+bug/1637974
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'hw/dma')
| -rw-r--r-- | hw/dma/pl080.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c index a7aacad..8f92550 100644 --- a/hw/dma/pl080.c +++ b/hw/dma/pl080.c @@ -229,7 +229,7 @@ static uint64_t pl080_read(void *opaque, hwaddr offset, i = (offset & 0xe0) >> 5; if (i >= s->nchannels) goto bad_offset; - switch (offset >> 2) { + switch ((offset >> 2) & 7) { case 0: /* SrcAddr */ return s->chan[i].src; case 1: /* DestAddr */ @@ -290,7 +290,7 @@ static void pl080_write(void *opaque, hwaddr offset, i = (offset & 0xe0) >> 5; if (i >= s->nchannels) goto bad_offset; - switch (offset >> 2) { + switch ((offset >> 2) & 7) { case 0: /* SrcAddr */ s->chan[i].src = value; break; @@ -308,6 +308,7 @@ static void pl080_write(void *opaque, hwaddr offset, pl080_run(s); break; } + return; } switch (offset >> 2) { case 2: /* IntTCClear */ |