diff options
| author | Paolo Bonzini <pbonzini@redhat.com> | 2014-12-29 14:48:14 +0100 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2024-01-18 10:43:13 +0100 |
| commit | 973a724eb006f674301a0c45f34b3c08dee0fe49 (patch) | |
| tree | 62c9aabc2a8c2f447232327f13167335dbcf8145 /hw/display/cirrus_vga.c | |
| parent | 9b53b95a1c3b46e5a54734a46f37790460c9265e (diff) | |
| download | qemu-973a724eb006f674301a0c45f34b3c08dee0fe49.zip qemu-973a724eb006f674301a0c45f34b3c08dee0fe49.tar.gz qemu-973a724eb006f674301a0c45f34b3c08dee0fe49.tar.bz2 | |
vga: implement horizontal pel panning in graphics modes
This implements smooth scrolling, as used for example by Commander Keen
and Second Reality.
Unfortunately, this is not enough to avoid tearing in Commander Keen,
because sometimes the wrong start address is used for a frame.
On real EGA, the panning register is sampled on every line, while
the display start is latched for the next frame at the start of the
vertical retrace. On real VGA, the panning register is also latched,
but at the end of the vertical retrace. It looks like Keen exploits
this by only waiting for horizontal retrace when setting the display
start, but implementing it breaks the 256-color Keen games...
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw/display/cirrus_vga.c')
| -rw-r--r-- | hw/display/cirrus_vga.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c index e637e5a..150883a 100644 --- a/hw/display/cirrus_vga.c +++ b/hw/display/cirrus_vga.c @@ -43,6 +43,7 @@ #include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "ui/pixel_ops.h" +#include "vga_regs.h" #include "cirrus_vga_internal.h" #include "qom/object.h" #include "ui/console.h" @@ -1121,6 +1122,9 @@ static void cirrus_get_params(VGACommonState *s1, params->line_compare = s->vga.cr[0x18] | ((s->vga.cr[0x07] & 0x10) << 4) | ((s->vga.cr[0x09] & 0x40) << 3); + + params->hpel = s->vga.ar[VGA_ATC_PEL]; + params->hpel_split = s->vga.ar[VGA_ATC_MODE] & 0x20; } static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s) |