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authorStefan Hajnoczi <stefanha@redhat.com>2025-03-10 13:40:48 +0800
committerStefan Hajnoczi <stefanha@redhat.com>2025-03-10 13:40:48 +0800
commit5136598e2667f35ef3dc1d757616a266bd5eb3a2 (patch)
tree6a6d40694034fee3078ce3497cc51762884ec30f /hw/core
parent2e14ac3c9ca25c974bb300c45c5b0303862c177d (diff)
parent8ff6ff09b9890ba390395d7510eca1025f7284df (diff)
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Merge tag 'accel-cpus-20250309' of https://github.com/philmd/qemu into staging
Generic CPUs / accelerators patch queue - Reduce "exec/tb-flush.h" inclusion on linux-user - Consider alignment in bsd-user's mmap_find_vma() - Unify MMAP common user emulation API - Simplify cpu-target.c further - Prefer cached CpuClass over CPU_GET_CLASS() macro - Restrict CPU has_work() handlers to system emulation - Consolidate core exec/vCPU section in MAINTAINERS # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmfN1NgACgkQ4+MsLN6t # wN6BghAAr5WBteo7OiNRyTA0Ilg+nOcTf6Re08CgWf/3TIMljEPq8o/tLQOxiFke # AMktDlvYTyg4BWa5UdAKLpj7N7eyHcXrqv95A6Lg/xoGdlbqfYIpyX7/5h0pV70f # z8WUj2/YMpoyXxvvAjw4YtUqHIWZhSTIBsFqJ6jALl6T7fouo8y++AWn/L+zY4tO # /qqC6djJwufphPJWm2NvG+nvf+T60C+4JUc8CkjYQsyL3K3HpoAgzrgb/6VRtHob # nKfORPboKEVSE1Z52GnmM9eMsZjbWOz9bkEN69yfRbHHQNuvsicok+V59PnWWDYd # JX6cC5ukJUJlgYDKOj2jCg9OouoV4mRYRqYYWPtE8WkGLoeJu4mV1AEkVB7h3lTA # BtUu4ohsrk/krfyB89apu8SqDPya6F4TDqJpGmAqlAG2UWJwrECuJV82uTDZql0R # MqnCUYb7OQBkdb9CoqFi47jTYlqgdVLKekS8udXLCaqWggki8Nb1GVQ09LFyv3NF # JlQVNNQG3D2V7JIDd2aXgr4PmhmV2oPv+HYxW+SPxU2qDHIU93krkKyi0TRk0mSC # sWvJYBJcwbXlnMD5clad1bTLZrK5Csl5WkX8I0d0feqeRPSXC2YBTwL2/GgzT8qF # n/2dxB3Lf+1LUl6KAv3kT9lONtqic0J9oBBcPUjVog2ikAD7+Vo= # =TZua # -----END PGP SIGNATURE----- # gpg: Signature made Mon 10 Mar 2025 01:50:16 HKT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'accel-cpus-20250309' of https://github.com/philmd/qemu: (38 commits) MAINTAINERS: Consolidate core exec/vCPU handling section cpus: Remove CPUClass::has_work() handler target/xtensa: Move has_work() from CPUClass to SysemuCPUOps target/tricore: Move has_work() from CPUClass to SysemuCPUOps target/sparc: Move has_work() from CPUClass to SysemuCPUOps target/sh4: Move has_work() from CPUClass to SysemuCPUOps target/s390x: Move has_work() from CPUClass to SysemuCPUOps target/s390x: Restrict I/O handler installers to system emulation target/rx: Move has_work() from CPUClass to SysemuCPUOps target/riscv: Move has_work() from CPUClass to SysemuCPUOps target/ppc: Move has_work() from CPUClass to SysemuCPUOps target/openrisc: Move has_work() from CPUClass to SysemuCPUOps target/mips: Move has_work() from CPUClass to SysemuCPUOps target/microblaze: Move has_work() from CPUClass to SysemuCPUOps target/m68k: Move has_work() from CPUClass to SysemuCPUOps target/loongarch: Move has_work() from CPUClass to SysemuCPUOps target/i386: Move has_work() from CPUClass to SysemuCPUOps target/hppa: Move has_work() from CPUClass to SysemuCPUOps target/hexagon: Remove CPUClass:has_work() handler target/avr: Move has_work() from CPUClass to SysemuCPUOps ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'hw/core')
-rw-r--r--hw/core/cpu-common.c47
-rw-r--r--hw/core/cpu-system.c179
-rw-r--r--hw/core/cpu-user.c17
3 files changed, 193 insertions, 50 deletions
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index d5cd227..9064dd2 100644
--- a/hw/core/cpu-common.c
+++ b/hw/core/cpu-common.c
@@ -40,9 +40,7 @@ CPUState *cpu_by_arch_id(int64_t id)
CPUState *cpu;
CPU_FOREACH(cpu) {
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->get_arch_id(cpu) == id) {
+ if (cpu->cc->get_arch_id(cpu) == id) {
return cpu;
}
}
@@ -101,11 +99,9 @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
void cpu_dump_state(CPUState *cpu, FILE *f, int flags)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->dump_state) {
+ if (cpu->cc->dump_state) {
cpu_synchronize_state(cpu);
- cc->dump_state(cpu, f, flags);
+ cpu->cc->dump_state(cpu, f, flags);
}
}
@@ -119,11 +115,10 @@ void cpu_reset(CPUState *cpu)
static void cpu_common_reset_hold(Object *obj, ResetType type)
{
CPUState *cpu = CPU(obj);
- CPUClass *cc = CPU_GET_CLASS(cpu);
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index);
- log_cpu_state(cpu, cc->reset_dump_flags);
+ log_cpu_state(cpu, cpu->cc->reset_dump_flags);
}
cpu->interrupt_request = 0;
@@ -139,11 +134,6 @@ static void cpu_common_reset_hold(Object *obj, ResetType type)
cpu_exec_reset_hold(cpu);
}
-static bool cpu_common_has_work(CPUState *cs)
-{
- return false;
-}
-
ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
{
ObjectClass *oc;
@@ -193,6 +183,20 @@ static void cpu_common_parse_features(const char *typename, char *features,
}
}
+bool cpu_exec_realizefn(CPUState *cpu, Error **errp)
+{
+ if (!accel_cpu_common_realize(cpu, errp)) {
+ return false;
+ }
+
+ /* Wait until cpu initialization complete before exposing cpu. */
+ cpu_list_add(cpu);
+
+ cpu_vmstate_register(cpu);
+
+ return true;
+}
+
static void cpu_common_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cpu = CPU(dev);
@@ -234,10 +238,24 @@ static void cpu_common_unrealizefn(DeviceState *dev)
cpu_exec_unrealizefn(cpu);
}
+void cpu_exec_unrealizefn(CPUState *cpu)
+{
+ cpu_vmstate_unregister(cpu);
+
+ cpu_list_remove(cpu);
+ /*
+ * Now that the vCPU has been removed from the RCU list, we can call
+ * accel_cpu_common_unrealize, which may free fields using call_rcu.
+ */
+ accel_cpu_common_unrealize(cpu);
+}
+
static void cpu_common_initfn(Object *obj)
{
CPUState *cpu = CPU(obj);
+ cpu_exec_class_post_init(CPU_GET_CLASS(obj));
+
/* cache the cpu class for the hotpath */
cpu->cc = CPU_GET_CLASS(cpu);
@@ -310,7 +328,6 @@ static void cpu_common_class_init(ObjectClass *klass, void *data)
k->parse_features = cpu_common_parse_features;
k->get_arch_id = cpu_common_get_arch_id;
- k->has_work = cpu_common_has_work;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c
index e511507..aed5076 100644
--- a/hw/core/cpu-system.c
+++ b/hw/core/cpu-system.c
@@ -21,18 +21,25 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "exec/address-spaces.h"
+#include "exec/cputlb.h"
#include "exec/memory.h"
+#include "exec/tb-flush.h"
#include "exec/tswap.h"
#include "hw/qdev-core.h"
#include "hw/qdev-properties.h"
#include "hw/core/sysemu-cpu-ops.h"
+#include "migration/vmstate.h"
+#include "system/tcg.h"
-bool cpu_paging_enabled(const CPUState *cpu)
+bool cpu_has_work(CPUState *cpu)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
+ return cpu->cc->sysemu_ops->has_work(cpu);
+}
- if (cc->sysemu_ops->get_paging_enabled) {
- return cc->sysemu_ops->get_paging_enabled(cpu);
+bool cpu_paging_enabled(const CPUState *cpu)
+{
+ if (cpu->cc->sysemu_ops->get_paging_enabled) {
+ return cpu->cc->sysemu_ops->get_paging_enabled(cpu);
}
return false;
@@ -41,10 +48,8 @@ bool cpu_paging_enabled(const CPUState *cpu)
bool cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
Error **errp)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->sysemu_ops->get_memory_mapping) {
- return cc->sysemu_ops->get_memory_mapping(cpu, list, errp);
+ if (cpu->cc->sysemu_ops->get_memory_mapping) {
+ return cpu->cc->sysemu_ops->get_memory_mapping(cpu, list, errp);
}
error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
@@ -54,15 +59,15 @@ bool cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
hwaddr paddr;
- if (cc->sysemu_ops->get_phys_page_attrs_debug) {
- paddr = cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs);
+ if (cpu->cc->sysemu_ops->get_phys_page_attrs_debug) {
+ paddr = cpu->cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr,
+ attrs);
} else {
/* Fallback for CPUs which don't implement the _attrs_ hook */
*attrs = MEMTXATTRS_UNSPECIFIED;
- paddr = cc->sysemu_ops->get_phys_page_debug(cpu, addr);
+ paddr = cpu->cc->sysemu_ops->get_phys_page_debug(cpu, addr);
}
/* Indicate that this is a debug access. */
attrs->debug = 1;
@@ -90,64 +95,53 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (!cc->sysemu_ops->write_elf32_qemunote) {
+ if (!cpu->cc->sysemu_ops->write_elf32_qemunote) {
return 0;
}
- return (*cc->sysemu_ops->write_elf32_qemunote)(f, cpu, opaque);
+ return (*cpu->cc->sysemu_ops->write_elf32_qemunote)(f, cpu, opaque);
}
int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (!cc->sysemu_ops->write_elf32_note) {
+ if (!cpu->cc->sysemu_ops->write_elf32_note) {
return -1;
}
- return (*cc->sysemu_ops->write_elf32_note)(f, cpu, cpuid, opaque);
+ return (*cpu->cc->sysemu_ops->write_elf32_note)(f, cpu, cpuid, opaque);
}
int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (!cc->sysemu_ops->write_elf64_qemunote) {
+ if (!cpu->cc->sysemu_ops->write_elf64_qemunote) {
return 0;
}
- return (*cc->sysemu_ops->write_elf64_qemunote)(f, cpu, opaque);
+ return (*cpu->cc->sysemu_ops->write_elf64_qemunote)(f, cpu, opaque);
}
int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (!cc->sysemu_ops->write_elf64_note) {
+ if (!cpu->cc->sysemu_ops->write_elf64_note) {
return -1;
}
- return (*cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque);
+ return (*cpu->cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque);
}
bool cpu_virtio_is_big_endian(CPUState *cpu)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->sysemu_ops->virtio_is_big_endian) {
- return cc->sysemu_ops->virtio_is_big_endian(cpu);
+ if (cpu->cc->sysemu_ops->virtio_is_big_endian) {
+ return cpu->cc->sysemu_ops->virtio_is_big_endian(cpu);
}
return target_words_bigendian();
}
GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
GuestPanicInformation *res = NULL;
- if (cc->sysemu_ops->get_crash_info) {
- res = cc->sysemu_ops->get_crash_info(cpu);
+ if (cpu->cc->sysemu_ops->get_crash_info) {
+ res = cpu->cc->sysemu_ops->get_crash_info(cpu);
}
return res;
}
@@ -189,8 +183,123 @@ void cpu_class_init_props(DeviceClass *dc)
device_class_set_props(dc, cpu_system_props);
}
+void cpu_exec_class_post_init(CPUClass *cc)
+{
+ /* Check mandatory SysemuCPUOps handlers */
+ g_assert(cc->sysemu_ops->has_work);
+}
+
void cpu_exec_initfn(CPUState *cpu)
{
cpu->memory = get_system_memory();
object_ref(OBJECT(cpu->memory));
}
+
+static int cpu_common_post_load(void *opaque, int version_id)
+{
+ if (tcg_enabled()) {
+ CPUState *cpu = opaque;
+
+ /*
+ * 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
+ * version_id is increased.
+ */
+ cpu->interrupt_request &= ~0x01;
+
+ tlb_flush(cpu);
+
+ /*
+ * loadvm has just updated the content of RAM, bypassing the
+ * usual mechanisms that ensure we flush TBs for writes to
+ * memory we've translated code from. So we must flush all TBs,
+ * which will now be stale.
+ */
+ tb_flush(cpu);
+ }
+
+ return 0;
+}
+
+static int cpu_common_pre_load(void *opaque)
+{
+ CPUState *cpu = opaque;
+
+ cpu->exception_index = -1;
+
+ return 0;
+}
+
+static bool cpu_common_exception_index_needed(void *opaque)
+{
+ CPUState *cpu = opaque;
+
+ return tcg_enabled() && cpu->exception_index != -1;
+}
+
+static const VMStateDescription vmstate_cpu_common_exception_index = {
+ .name = "cpu_common/exception_index",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = cpu_common_exception_index_needed,
+ .fields = (const VMStateField[]) {
+ VMSTATE_INT32(exception_index, CPUState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static bool cpu_common_crash_occurred_needed(void *opaque)
+{
+ CPUState *cpu = opaque;
+
+ return cpu->crash_occurred;
+}
+
+static const VMStateDescription vmstate_cpu_common_crash_occurred = {
+ .name = "cpu_common/crash_occurred",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = cpu_common_crash_occurred_needed,
+ .fields = (const VMStateField[]) {
+ VMSTATE_BOOL(crash_occurred, CPUState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+const VMStateDescription vmstate_cpu_common = {
+ .name = "cpu_common",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .pre_load = cpu_common_pre_load,
+ .post_load = cpu_common_post_load,
+ .fields = (const VMStateField[]) {
+ VMSTATE_UINT32(halted, CPUState),
+ VMSTATE_UINT32(interrupt_request, CPUState),
+ VMSTATE_END_OF_LIST()
+ },
+ .subsections = (const VMStateDescription * const []) {
+ &vmstate_cpu_common_exception_index,
+ &vmstate_cpu_common_crash_occurred,
+ NULL
+ }
+};
+
+void cpu_vmstate_register(CPUState *cpu)
+{
+ if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
+ vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
+ }
+ if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) {
+ vmstate_register(NULL, cpu->cpu_index,
+ cpu->cc->sysemu_ops->legacy_vmsd, cpu);
+ }
+}
+
+void cpu_vmstate_unregister(CPUState *cpu)
+{
+ if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) {
+ vmstate_unregister(NULL, cpu->cc->sysemu_ops->legacy_vmsd, cpu);
+ }
+ if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
+ vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
+ }
+}
diff --git a/hw/core/cpu-user.c b/hw/core/cpu-user.c
index cdd8de2..7176791 100644
--- a/hw/core/cpu-user.c
+++ b/hw/core/cpu-user.c
@@ -10,6 +10,7 @@
#include "hw/qdev-core.h"
#include "hw/qdev-properties.h"
#include "hw/core/cpu.h"
+#include "migration/vmstate.h"
static const Property cpu_user_props[] = {
/*
@@ -26,7 +27,23 @@ void cpu_class_init_props(DeviceClass *dc)
device_class_set_props(dc, cpu_user_props);
}
+void cpu_exec_class_post_init(CPUClass *cc)
+{
+ /* nothing to do */
+}
+
void cpu_exec_initfn(CPUState *cpu)
{
/* nothing to do */
}
+
+void cpu_vmstate_register(CPUState *cpu)
+{
+ assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
+ qdev_get_vmsd(DEVICE(cpu))->unmigratable);
+}
+
+void cpu_vmstate_unregister(CPUState *cpu)
+{
+ /* nothing to do */
+}