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| author | Alexandra Diupina <adiupina@astralinux.ru> | 2024-10-14 17:05:51 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-10-15 11:29:45 +0100 |
| commit | 3db74afec3ca87f81fbdf5918ed1e21d837fbfab (patch) | |
| tree | 7bca257d335ec3571e77a427975df149964ad9d8 /hw/core | |
| parent | 12dc8f6eca1ead876142fd3d6731cf3da1295f2a (diff) | |
| download | qemu-3db74afec3ca87f81fbdf5918ed1e21d837fbfab.zip qemu-3db74afec3ca87f81fbdf5918ed1e21d837fbfab.tar.gz qemu-3db74afec3ca87f81fbdf5918ed1e21d837fbfab.tar.bz2 | |
hw/intc/arm_gicv3_cpuif: Add cast to match the documentation
The result of 1 << regbit with regbit==31 has a 1 in the 32nd bit.
When cast to uint64_t (for further bitwise OR), the 32 most
significant bits will be filled with 1s. However, the documentation
states that the upper 32 bits of ICH_AP[0/1]R<n>_EL2 are reserved.
Add an explicit cast to match the documentation.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Cc: qemu-stable@nongnu.org
Fixes: c3f21b065a ("hw/intc/arm_gicv3_cpuif: Support vLPIs")
Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/core')
0 files changed, 0 insertions, 0 deletions