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| author | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2021-09-03 12:32:17 +0100 |
|---|---|---|
| committer | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2021-09-08 11:09:45 +0100 |
| commit | 8e8aa96590156577ed8a2623d1a2e4db4e5748b8 (patch) | |
| tree | 71447f3a27d0bcf3d89bb809eac46e646207a305 /hw/char | |
| parent | 9d248a4be524a6c820634e9b58e79085972cb78f (diff) | |
| download | qemu-8e8aa96590156577ed8a2623d1a2e4db4e5748b8.zip qemu-8e8aa96590156577ed8a2623d1a2e4db4e5748b8.tar.gz qemu-8e8aa96590156577ed8a2623d1a2e4db4e5748b8.tar.bz2 | |
escc: introduce escc_soft_reset_chn() for software reset
This new software reset function is to be called when the appropriate channel
software reset bit is written to register WR9. Its initial implementation is
the same as the existing escc_reset_chn() function used for device reset.
Add a new trace event when the guest initiates a soft reset via the WR9 register
to help diagnose guest reset issues.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210903113223.19551-4-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Diffstat (limited to 'hw/char')
| -rw-r--r-- | hw/char/escc.c | 40 | ||||
| -rw-r--r-- | hw/char/trace-events | 1 |
2 files changed, 39 insertions, 2 deletions
diff --git a/hw/char/escc.c b/hw/char/escc.c index b0d3b92..697f15f 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -297,6 +297,40 @@ static void escc_reset_chn(ESCCChannelState *s) clear_queue(s); } +static void escc_soft_reset_chn(ESCCChannelState *s) +{ + int i; + + s->reg = 0; + for (i = 0; i < ESCC_SERIAL_REGS; i++) { + s->rregs[i] = 0; + s->wregs[i] = 0; + } + /* 1X divisor, 1 stop bit, no parity */ + s->wregs[W_TXCTRL1] = TXCTRL1_1STOP; + s->wregs[W_MINTR] = MINTR_RST_ALL; + /* Synch mode tx clock = TRxC */ + s->wregs[W_CLOCK] = CLOCK_TRXC; + /* PLL disabled */ + s->wregs[W_MISC2] = MISC2_PLLDIS; + /* Enable most interrupts */ + s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | + EXTINT_TXUNDRN | EXTINT_BRKINT; + if (s->disabled) { + s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | + STATUS_CTS | STATUS_TXUNDRN; + } else { + s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_TXUNDRN; + } + s->rregs[R_SPEC] = SPEC_BITS8 | SPEC_ALLSENT; + + s->rx = s->tx = 0; + s->rxint = s->txint = 0; + s->rxint_under_svc = s->txint_under_svc = 0; + s->e0_mode = s->led_mode = s->caps_lock_mode = s->num_lock_mode = 0; + clear_queue(s); +} + static void escc_reset(DeviceState *d) { ESCCState *s = ESCC(d); @@ -547,10 +581,12 @@ static void escc_mem_write(void *opaque, hwaddr addr, default: break; case MINTR_RST_B: - escc_reset_chn(&serial->chn[0]); + trace_escc_soft_reset_chn(CHN_C(&serial->chn[0])); + escc_soft_reset_chn(&serial->chn[0]); return; case MINTR_RST_A: - escc_reset_chn(&serial->chn[1]); + trace_escc_soft_reset_chn(CHN_C(&serial->chn[1])); + escc_soft_reset_chn(&serial->chn[1]); return; case MINTR_RST_ALL: escc_reset(DEVICE(serial)); diff --git a/hw/char/trace-events b/hw/char/trace-events index 1436fb4..073f98e 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -36,6 +36,7 @@ grlib_apbuart_writel_unknown(uint64_t addr, uint32_t value) "addr 0x%"PRIx64" va grlib_apbuart_readl_unknown(uint64_t addr) "addr 0x%"PRIx64 # escc.c +escc_soft_reset_chn(char channel) "soft reset channel %c" escc_put_queue(char channel, int b) "channel %c put: 0x%02x" escc_get_queue(char channel, int val) "channel %c get 0x%02x" escc_update_irq(int irq) "IRQ = %d" |