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| author | Peter Maydell <peter.maydell@linaro.org> | 2012-12-11 11:30:37 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-12-11 11:30:37 +0000 |
| commit | ee3f095680e4f578f4f1371a90acc20375b48966 (patch) | |
| tree | 84dbe2196110839a10a975a95ffe5c7f6e06b880 /hw/arm_gic_common.c | |
| parent | cad065f18e1ca7694385f42f560da637d4e651b6 (diff) | |
| download | qemu-ee3f095680e4f578f4f1371a90acc20375b48966.zip qemu-ee3f095680e4f578f4f1371a90acc20375b48966.tar.gz qemu-ee3f095680e4f578f4f1371a90acc20375b48966.tar.bz2 | |
hw/arm_gic_common: Correct GICC_PMR reset value for newer GICs
The GIC architecture specification for v1 and v2 GICs (as found
on the Cortex-A9 and newer) states that the GICC_PMR reset value
is zero; this differs from the 0xf0 reset value used on 11MPCore.
The NVIC is different again in not having a CPU interface; since
we share the GIC code we must force the priority mask field to
allow through all interrupts.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Igor Mitsyanko <i.mitsyanko@samsung.com>
Diffstat (limited to 'hw/arm_gic_common.c')
| -rw-r--r-- | hw/arm_gic_common.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/hw/arm_gic_common.c b/hw/arm_gic_common.c index 8369309..73ae331 100644 --- a/hw/arm_gic_common.c +++ b/hw/arm_gic_common.c @@ -127,7 +127,11 @@ static void arm_gic_common_reset(DeviceState *dev) int i; memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state)); for (i = 0 ; i < s->num_cpu; i++) { - s->priority_mask[i] = 0xf0; + if (s->revision == REV_11MPCORE) { + s->priority_mask[i] = 0xf0; + } else { + s->priority_mask[i] = 0; + } s->current_pending[i] = 1023; s->running_irq[i] = 1023; s->running_priority[i] = 0x100; |