From ee3f095680e4f578f4f1371a90acc20375b48966 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 11 Dec 2012 11:30:37 +0000 Subject: hw/arm_gic_common: Correct GICC_PMR reset value for newer GICs The GIC architecture specification for v1 and v2 GICs (as found on the Cortex-A9 and newer) states that the GICC_PMR reset value is zero; this differs from the 0xf0 reset value used on 11MPCore. The NVIC is different again in not having a CPU interface; since we share the GIC code we must force the priority mask field to allow through all interrupts. Signed-off-by: Peter Maydell Reviewed-by: Igor Mitsyanko --- hw/arm_gic_common.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'hw/arm_gic_common.c') diff --git a/hw/arm_gic_common.c b/hw/arm_gic_common.c index 8369309..73ae331 100644 --- a/hw/arm_gic_common.c +++ b/hw/arm_gic_common.c @@ -127,7 +127,11 @@ static void arm_gic_common_reset(DeviceState *dev) int i; memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state)); for (i = 0 ; i < s->num_cpu; i++) { - s->priority_mask[i] = 0xf0; + if (s->revision == REV_11MPCORE) { + s->priority_mask[i] = 0xf0; + } else { + s->priority_mask[i] = 0; + } s->current_pending[i] = 1023; s->running_irq[i] = 1023; s->running_priority[i] = 0x100; -- cgit v1.1