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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2024-05-24 14:08:36 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-05-30 13:21:06 +0100 |
| commit | f271877307f1bb43ac4031bf6d962bdd86caa498 (patch) | |
| tree | 96baa30ca22b8cbcba3c7fe12d3cf50b64d36ac8 /hw/arm | |
| parent | d9aff83ad569714ec1b05176942a80fd80e062b7 (diff) | |
| download | qemu-f271877307f1bb43ac4031bf6d962bdd86caa498.zip qemu-f271877307f1bb43ac4031bf6d962bdd86caa498.tar.gz qemu-f271877307f1bb43ac4031bf6d962bdd86caa498.tar.bz2 | |
hw/arm/xilinx_zynq: Add cache controller
The Zynq 7000 SoCs contain a CoreLink L2C-310 cache controller. Add the
corresponding Qemu device to the xilinx-zynq-a9 machine.
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Message-id: 20240524120837.10057-2-sebastian.huber@embedded-brains.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm')
| -rw-r--r-- | hw/arm/Kconfig | 1 | ||||
| -rw-r--r-- | hw/arm/xilinx_zynq.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 8b97683..1ad60da 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -370,6 +370,7 @@ config ZYNQ select A9MPCORE select CADENCE # UART select PFLASH_CFI02 + select PL310 # cache controller select PL330 select SDHCI select SSI_M25P80 diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index fc3abcb..0abb62f 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -241,6 +241,7 @@ static void zynq_init(MachineState *machine) busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); + sysbus_create_varargs("l2x0", MPCORE_PERIPHBASE + 0x2000, NULL); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); sysbus_connect_irq(busdev, 1, |