diff options
| author | Jamin Lin <jamin_lin@aspeedtech.com> | 2024-07-04 16:29:19 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2024-07-09 08:05:44 +0200 |
| commit | f2146bc6cb98e3e6d5749a6a974a53a1a1a754fc (patch) | |
| tree | 6366d57b3416c2347aa68a2a82128d05de92b7b1 /hw/arm | |
| parent | 2095468d2cce73d1d3825cb953bd5114fffe73c8 (diff) | |
| download | qemu-f2146bc6cb98e3e6d5749a6a974a53a1a1a754fc.zip qemu-f2146bc6cb98e3e6d5749a6a974a53a1a1a754fc.tar.gz qemu-f2146bc6cb98e3e6d5749a6a974a53a1a1a754fc.tar.bz2 | |
aspeed/soc: set dma64 property for AST2700 ftgmac100
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
And the base address of dram is "0x4 00000000" which
is 64bits address.
Set dma64 property for ftgmac100 model to support
64bits dram address DMA.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'hw/arm')
| -rw-r--r-- | hw/arm/aspeed_ast27x0.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 18e6a8b..a9fb0d4 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -552,9 +552,12 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) return; } + /* Net */ for (i = 0; i < sc->macs_num; i++) { object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, &error_abort); + object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true, + &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { return; } |