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authorCédric Le Goater <clg@kaod.org>2021-10-12 08:20:08 +0200
committerCédric Le Goater <clg@kaod.org>2021-10-12 08:20:08 +0200
commit602610383f1be927830b903275ee02fcd368d6e8 (patch)
tree5963926690cf2bff33d5f9ae8cac6494979af197 /hw/arm
parent33456a8870f761ae4aba223a65082985d870bfc7 (diff)
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aspeed/i2c: QOMify AspeedI2CBus
Introduce an AspeedI2CBus SysBusDevice model and attach the associated memory region and IRQ to the newly instantiated objects. Before this change, the I2C bus IRQs were all attached to the SysBusDevice model of the I2C controller. Adapt the AST2600 SoC realize routine to take into account this change. Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'hw/arm')
-rw-r--r--hw/arm/aspeed_ast2600.c7
1 files changed, 2 insertions, 5 deletions
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index c69f27d..a70e4c4 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -337,11 +337,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
sc->irqmap[ASPEED_DEV_I2C] + i);
- /*
- * The AST2600 SoC has one IRQ per I2C bus. Skip the common
- * IRQ (AST2400 and AST2500) and connect all bussses.
- */
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq);
+ /* The AST2600 I2C controller has one IRQ per bus. */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
}
/* FMC, The number of CS is set at the board level */