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| author | Cédric Le Goater <clg@kaod.org> | 2019-09-25 16:32:47 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-10-15 18:09:05 +0100 |
| commit | 289251b033979234ed735a7b996a187880ed090e (patch) | |
| tree | 6abd4d0a0e1c6530e934bdba140c7ddefde17c79 /hw/arm | |
| parent | d300db02774b2225cd8a527ee6212e093e94fdce (diff) | |
| download | qemu-289251b033979234ed735a7b996a187880ed090e.zip qemu-289251b033979234ed735a7b996a187880ed090e.tar.gz qemu-289251b033979234ed735a7b996a187880ed090e.tar.bz2 | |
aspeed: add support for the Aspeed MII controller of the AST2600
The AST2600 SoC has an extra controller to set the PHY registers.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190925143248.10000-23-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm')
| -rw-r--r-- | hw/arm/aspeed_ast2600.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 25d2c2d..af04746 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -31,6 +31,10 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { [ASPEED_FMC] = 0x1E620000, [ASPEED_SPI1] = 0x1E630000, [ASPEED_SPI2] = 0x1E641000, + [ASPEED_MII1] = 0x1E650000, + [ASPEED_MII2] = 0x1E650008, + [ASPEED_MII3] = 0x1E650010, + [ASPEED_MII4] = 0x1E650018, [ASPEED_ETH1] = 0x1E660000, [ASPEED_ETH3] = 0x1E670000, [ASPEED_ETH2] = 0x1E680000, @@ -181,6 +185,12 @@ static void aspeed_soc_ast2600_init(Object *obj) for (i = 0; i < sc->macs_num; i++) { sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]), sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); + + sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]), + TYPE_ASPEED_MII); + object_property_add_const_link(OBJECT(&s->mii[i]), "nic", + OBJECT(&s->ftgmac100[i]), + &error_abort); } sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma), @@ -417,6 +427,16 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) sc->memmap[ASPEED_ETH1 + i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); + + object_property_set_bool(OBJECT(&s->mii[i]), true, "realized", + &err); + if (err) { + error_propagate(errp, err); + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, + sc->memmap[ASPEED_MII1 + i]); } /* XDMA */ |