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| author | Joel Stanley <joel@jms.id.au> | 2020-09-18 09:04:36 +0200 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2020-09-18 09:04:36 +0200 |
| commit | 204dab83fe00a3e0781d93ad7899192a9409e987 (patch) | |
| tree | 521157d2cda89faa02f4a3c31e073dc7e387e1cd /hw/arm | |
| parent | 9820e52fbef71564d05f3a83a26ce4c3f7d5d3fd (diff) | |
| download | qemu-204dab83fe00a3e0781d93ad7899192a9409e987.zip qemu-204dab83fe00a3e0781d93ad7899192a9409e987.tar.gz qemu-204dab83fe00a3e0781d93ad7899192a9409e987.tar.bz2 | |
misc: aspeed_scu: Update AST2600 silicon id register
Aspeed have released an updated datasheet (v7) containing the silicon id
for the AST2600 A2. It looks like this:
SCU004 SCU014
AST2600-A0 0x05000303 0x05000303
AST2600-A1 0x05010303 0x05010303
AST2600-A2 0x05010303 0x05020303
AST2620-A1 0x05010203 0x05010203
AST2620-A2 0x05010203 0x05020203
The SCU004 (silicon id 1) value matches SCU014 for A0, but for
subsequent revisions it is hard coded to the A1 value.
Qemu effectively dropped support for the A0 in 7582591ae745 ("aspeed:
Support AST2600A1 silicon revision") as the A0 reset table was removed,
so it makes sense to only support the behaviour of A1 and onwards.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200916082012.776628-1-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'hw/arm')
0 files changed, 0 insertions, 0 deletions