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| author | Patrick Williams <patrick@stwcx.xyz> | 2022-10-24 11:20:15 +0200 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-10-24 11:20:15 +0200 |
| commit | 104bdaffd753042c652a3731753fc3b391e32d87 (patch) | |
| tree | 44bcde2efade24143a4338a26f4b949521322eec /hw/arm | |
| parent | e5c1b489acac6e2d264c67d5c0665ef940f85e86 (diff) | |
| download | qemu-104bdaffd753042c652a3731753fc3b391e32d87.zip qemu-104bdaffd753042c652a3731753fc3b391e32d87.tar.gz qemu-104bdaffd753042c652a3731753fc3b391e32d87.tar.bz2 | |
hw/arm/aspeed: increase Bletchley memory size
For the PVT-class hardware we have increased the memory size of
this device to 2 GiB. Adjust the device model accordingly.
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20221007110529.3657749-1-patrick@stwcx.xyz>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'hw/arm')
| -rw-r--r-- | hw/arm/aspeed.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index bc3ecdb..bc5c1e1 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1330,6 +1330,13 @@ static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) aspeed_soc_num_cpus(amc->soc_name); }; +/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ +#if HOST_LONG_BITS == 32 +#define BLETCHLEY_BMC_RAM_SIZE (1 * GiB) +#else +#define BLETCHLEY_BMC_RAM_SIZE (2 * GiB) +#endif + static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -1344,7 +1351,7 @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) amc->num_cs = 2; amc->macs_mask = ASPEED_MAC2_ON; amc->i2c_init = bletchley_bmc_i2c_init; - mc->default_ram_size = 512 * MiB; + mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE; mc->default_cpus = mc->min_cpus = mc->max_cpus = aspeed_soc_num_cpus(amc->soc_name); } |