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| author | Mostafa Saleh <smostafa@google.com> | 2024-07-15 08:45:12 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-07-18 13:49:29 +0100 |
| commit | 1ea8a6f59b8d6dbcc5d0aa59380ae45a18231b88 (patch) | |
| tree | d9f2fa31801fa1ef2a419643225e229ed103c909 /hw/arm/trace-events | |
| parent | f42a0a57c0a22210456e83676f43e88782e43942 (diff) | |
| download | qemu-1ea8a6f59b8d6dbcc5d0aa59380ae45a18231b88.zip qemu-1ea8a6f59b8d6dbcc5d0aa59380ae45a18231b88.tar.gz qemu-1ea8a6f59b8d6dbcc5d0aa59380ae45a18231b88.tar.bz2 | |
hw/arm/smmu: Support nesting in smmuv3_range_inval()
With nesting, we would need to invalidate IPAs without
over-invalidating stage-1 IOVAs. This can be done by
distinguishing IPAs in the TLBs by having ASID=-1.
To achieve that, rework the invalidation for IPAs to have a
separate function, while for IOVA invalidation ASID=-1 means
invalidate for all ASIDs.
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20240715084519.1189624-13-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/trace-events')
| -rw-r--r-- | hw/arm/trace-events | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 09ccd39..7d9c170 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -46,7 +46,7 @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%x - end=0x%x" smmuv3_cmdq_cfgi_cd(uint32_t sid) "sid=0x%x" smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid=0x%x (hits=%d, misses=%d, hit rate=%d)" smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid=0x%x (hits=%d, misses=%d, hit rate=%d)" -smmuv3_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid=%d asid=%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d" +smmuv3_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf, int stage) "vmid=%d asid=%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d stage=%d" smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(int asid) "asid=%d" smmuv3_cmdq_tlbi_s12_vmid(int vmid) "vmid=%d" |