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authorNikita Ostrenkov <n.ostrenkov@gmail.com>2024-01-08 14:32:58 +0000
committerPeter Maydell <peter.maydell@linaro.org>2024-01-09 14:42:39 +0000
commitf7f5784af19155df658237d1aae04297d371402b (patch)
treefcdbe6fc81bd419969f8f45d3c89014f7772640a /hw/arm/fsl-imx6.c
parent9468484fe904ab4691de6d9c34616667f377ceac (diff)
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hw/arm: add cache controller for Freescale i.MX6
Signed-off-by: Nikita Ostrenkov <n.ostrenkov@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20231219105510.4907-1-n.ostrenkov@gmail.com [PMM: fixed stray whitespace] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/fsl-imx6.c')
-rw-r--r--hw/arm/fsl-imx6.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index b215302..af2e982 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -154,6 +154,9 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
}
+ /* L2 cache controller */
+ sysbus_create_simple("l2x0", FSL_IMX6_PL310_ADDR, NULL);
+
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) {
return;
}