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authorBernhard Beschow <shentey@gmail.com>2025-01-11 19:37:02 +0100
committerPeter Maydell <peter.maydell@linaro.org>2025-01-27 13:50:14 +0000
commit1b326f278d05543425a71165a66b925922e532ac (patch)
treec84350f3f8e13ce6ea0f0575273f0700f0c8e540 /hw/arm/fsl-imx6.c
parenta451cc11c47903242123def2717a86a56e5fb390 (diff)
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hw/pci-host/designware: Expose MSI IRQ
Fixes INTD and MSI interrupts poking the same IRQ line without keeping track of each other's IRQ level. Furthermore, SoCs such as the i.MX 8M Plus don't share the MSI IRQ with the INTx lines, so expose it as a dedicated pin. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/fsl-imx6.c')
-rw-r--r--hw/arm/fsl-imx6.c13
1 files changed, 12 insertions, 1 deletions
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index ac8c66e..88b9ccf 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -106,6 +106,8 @@ static void fsl_imx6_init(Object *obj)
object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET);
object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
+ object_initialize_child(obj, "pcie4-msi-irq", &s->pcie4_msi_irq,
+ TYPE_OR_IRQ);
}
static void fsl_imx6_realize(DeviceState *dev, Error **errp)
@@ -435,14 +437,23 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX6_PCIe_REG_ADDR);
+ object_property_set_int(OBJECT(&s->pcie4_msi_irq), "num-lines", 2,
+ &error_abort);
+ qdev_realize(DEVICE(&s->pcie4_msi_irq), NULL, &error_abort);
+
+ irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE4_MSI_IRQ);
+ qdev_connect_gpio_out(DEVICE(&s->pcie4_msi_irq), 0, irq);
+
irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE1_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq);
irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE2_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq);
irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE3_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq);
- irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE4_IRQ);
+ irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 0);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
+ irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 1);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4, irq);
/*
* PCIe PHY