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author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-10-24 18:24:18 +0200 |
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committer | Cédric Le Goater <clg@kaod.org> | 2023-10-25 09:52:44 +0200 |
commit | 1a94fae4c18aacc563a6c6bf61aa7f357f1e2eb0 (patch) | |
tree | 2b7d9561f07fc37bb9e49565ff485ef442e8672e /hw/arm/aspeed_soc_common.c | |
parent | 4fc5e8065b3632cec2b9cfbb62b3b4d053660576 (diff) | |
download | qemu-1a94fae4c18aacc563a6c6bf61aa7f357f1e2eb0.zip qemu-1a94fae4c18aacc563a6c6bf61aa7f357f1e2eb0.tar.gz qemu-1a94fae4c18aacc563a6c6bf61aa7f357f1e2eb0.tar.bz2 |
hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC
TYPE_ASPEED2400_SOC inherits from TYPE_ASPEED_SOC.
In few commits we'll add more fields, but to keep
review process simple, don't add any yet.
TYPE_ASPEED_SOC is common to various Aspeed SoCs,
define it in aspeed_soc_common.c.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'hw/arm/aspeed_soc_common.c')
-rw-r--r-- | hw/arm/aspeed_soc_common.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index a43f5d2..b66f769 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -12,6 +12,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" +#include "hw/qdev-properties.h" #include "hw/misc/unimp.h" #include "hw/arm/aspeed_soc.h" #include "hw/char/serial.h" @@ -112,3 +113,31 @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, memory_region_add_subregion_overlap(s->memory, addr, sysbus_mmio_get_region(dev, 0), -1000); } + +static Property aspeed_soc_properties[] = { + DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_END_OF_LIST(), +}; + +static void aspeed_soc_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + device_class_set_props(dc, aspeed_soc_properties); +} + +static const TypeInfo aspeed_soc_types[] = { + { + .name = TYPE_ASPEED_SOC, + .parent = TYPE_DEVICE, + .instance_size = sizeof(AspeedSoCState), + .class_size = sizeof(AspeedSoCClass), + .class_init = aspeed_soc_class_init, + .abstract = true, + }, +}; + +DEFINE_TYPES(aspeed_soc_types) |