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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-07-11 13:11:32 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-07-11 13:11:32 +0100 |
| commit | 3cfcc329afd99138e654b65f6f49156fca2e8cdd (patch) | |
| tree | 8d5a6393fb486352ad967fbe47f2e4dcb42927f7 /hw/arm/aspeed.c | |
| parent | 42e1d798a6a01817bdcf722ac27eea01531e21cd (diff) | |
| parent | 05449abb1d4c5f0c69ceb3d8d03cbc75de39b646 (diff) | |
| download | qemu-3cfcc329afd99138e654b65f6f49156fca2e8cdd.zip qemu-3cfcc329afd99138e654b65f6f49156fca2e8cdd.tar.gz qemu-3cfcc329afd99138e654b65f6f49156fca2e8cdd.tar.bz2 | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210709' into staging
target-arm queue:
* New machine type: stm32vldiscovery
* hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
* hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
* virt: Fix implementation of GPIO-based powerdown/shutdown mechanism
* Correct the encoding of MDCCSR_EL0 and DBGDSCRint
* hw/intc: Improve formatting of MEMTX_ERROR guest error message
# gpg: Signature made Fri 09 Jul 2021 17:09:10 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210709:
hw/intc: Improve formatting of MEMTX_ERROR guest error message
target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint
hw/arm/stellaris: Expand comment about handling of OLED chipselect
hw/gpio/pl061: Document a shortcoming in our implementation
hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset
hw/arm/virt: Make PL061 GPIO lines pulled low, not high
hw/gpio/pl061: Make pullup/pulldown of outputs configurable
hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
hw/gpio/pl061: Document the interface of this device
hw/gpio/pl061: Add tracepoints for register read and write
hw/gpio/pl061: Clean up read/write offset handling logic
hw/gpio/pl061: Convert DPRINTF to tracepoints
hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
tests/boot-serial-test: Add STM32VLDISCOVERY board testcase
docs/system: arm: Add stm32 boards description
stm32vldiscovery: Add the STM32VLDISCOVERY Machine
stm32f100: Add the stm32f100 SoC
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/aspeed.c')
0 files changed, 0 insertions, 0 deletions