diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2021-06-16 17:02:30 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-06-16 17:02:30 +0100 |
| commit | 38848ce565849e5b867a5e08022b3c755039c11a (patch) | |
| tree | 8e2f7b8f7d94069e3e33a7f87303acd7459932d7 /hw/arm/aspeed.c | |
| parent | e3897b75fd2ac8c4bfda95d60309cb6414da8000 (diff) | |
| parent | 703235a303d6862a7e3f5c6aa9eff7471cb138b2 (diff) | |
| download | qemu-38848ce565849e5b867a5e08022b3c755039c11a.zip qemu-38848ce565849e5b867a5e08022b3c755039c11a.tar.gz qemu-38848ce565849e5b867a5e08022b3c755039c11a.tar.bz2 | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210616' into staging
target-arm queue:
* hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes
* handle some UNALLOCATED decode cases correctly rather
than asserting
* hw: virt: consider hw_compat_6_0
* hw/arm: add quanta-gbs-bmc machine
* hw/intc/armv7m_nvic: Remove stale comment
* target/arm: Fix mte page crossing test
* hw/arm: quanta-q71l add pca954x muxes
* target/arm: First few parts of MVE support
# gpg: Signature made Wed 16 Jun 2021 14:34:49 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210616: (25 commits)
include/qemu/int128.h: Add function to create Int128 from int64_t
bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations
target/arm: Move expand_pred_b() data to vec_helper.c
target/arm: Add framework for MVE decode
target/arm: Implement MVE LETP insn
target/arm: Implement MVE DLSTP
target/arm: Implement MVE WLSTP insn
target/arm: Implement MVE LCTP
target/arm: Let vfp_access_check() handle late NOCP checks
target/arm: Add handling for PSR.ECI/ICI
target/arm: Handle VPR semantics in existing code
target/arm: Enable FPSCR.QC bit for MVE
target/arm: Provide and use H8 and H1_8 macros
hw/arm: quanta-q71l add pca954x muxes
hw/arm: gsj add pca9548
hw/arm: gsj add i2c comments
target/arm: Fix mte page crossing test
hw/intc/armv7m_nvic: Remove stale comment
hw/arm: quanta-gbs-bmc add i2c comments
hw/arm: add quanta-gbs-bmc machine
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/aspeed.c')
| -rw-r--r-- | hw/arm/aspeed.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 0eafc79..1301e8f 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -14,6 +14,7 @@ #include "hw/arm/boot.h" #include "hw/arm/aspeed.h" #include "hw/arm/aspeed_soc.h" +#include "hw/i2c/i2c_mux_pca954x.h" #include "hw/i2c/smbus_eeprom.h" #include "hw/misc/pca9552.h" #include "hw/misc/tmp105.h" @@ -461,14 +462,18 @@ static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ /* TODO: Add Memory Riser i2c mux and eeproms. */ - /* TODO: i2c-2: pca9546@74 */ - /* TODO: i2c-2: pca9548@77 */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); + /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ - /* TODO: i2c-7: Add pca9546@70 */ + + /* i2c-7 */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); /* - i2c@0: pmbus@59 */ /* - i2c@1: pmbus@58 */ /* - i2c@2: pmbus@58 */ /* - i2c@3: pmbus@59 */ + /* TODO: i2c-7: Add PDB FRU eeprom@52 */ /* TODO: i2c-8: Add BMC FRU eeprom@50 */ } |