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| author | Peter Maydell <peter.maydell@linaro.org> | 2018-04-26 11:56:57 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-04-26 11:56:57 +0100 |
| commit | 20b2323edf8d42fe024902ca7d847b9f71c98df1 (patch) | |
| tree | 5659345455e517291d54c7f552c9cd364c208993 /hw/arm/aspeed.c | |
| parent | 569df5b6e118128995c70d266668f11825c8fec8 (diff) | |
| parent | fbf32752663878947de455ff57cb5b9318f14bec (diff) | |
| download | qemu-20b2323edf8d42fe024902ca7d847b9f71c98df1.zip qemu-20b2323edf8d42fe024902ca7d847b9f71c98df1.tar.gz qemu-20b2323edf8d42fe024902ca7d847b9f71c98df1.tar.bz2 | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180426' into staging
target-arm queue:
* xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo
* timer/aspeed: fix vmstate version id
* hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAM
* hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate'
* hw/arm/highbank: don't make sysram 'nomigrate'
* hw/arm/raspi: Don't bother setting default_cpu_type
* PMU emulation: some minor bugfixes and preparation for
support of other events than just the cycle counter
* target/arm: Use v7m_stack_read() for reading the frame signature
* target/arm: Remove stale TODO comment
* arm: always start from first_cpu when registering loader cpu reset callback
* device_tree: Increase FDT_MAX_SIZE to 1 MiB
# gpg: Signature made Thu 26 Apr 2018 11:46:31 BST
# gpg: using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20180426:
xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo
timer/aspeed: fix vmstate version id
hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAM
hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate'
hw/arm/highbank: don't make sysram 'nomigrate'
hw/arm/raspi: Don't bother setting default_cpu_type
target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide
target/arm: Fix bitmask for PMCCFILTR writes
target/arm: Allow EL change hooks to do IO
target/arm: Add pre-EL change hooks
target/arm: Support multiple EL change hooks
target/arm: Fetch GICv3 state directly from CPUARMState
target/arm: Mask PMU register writes based on PMCR_EL0.N
target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0
target/arm: Check PMCNTEN for whether PMCCNTR is enabled
target/arm: Use v7m_stack_read() for reading the frame signature
target/arm: Remove stale TODO comment
arm: always start from first_cpu when registering loader cpu reset callback
device_tree: Increase FDT_MAX_SIZE to 1 MiB
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/aspeed.c')
| -rw-r--r-- | hw/arm/aspeed.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 7088c90..aecb3c1 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -225,7 +225,7 @@ static void aspeed_board_init(MachineState *machine, * SoC and 128MB for the AST2500 SoC, which is twice as big as * needed by the flash modules of the Aspeed machines. */ - memory_region_init_rom_nomigrate(boot_rom, OBJECT(bmc), "aspeed.boot_rom", + memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", fl->size, &error_abort); memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, boot_rom); |