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authorMichael S. Tsirkin <mst@redhat.com>2009-11-11 14:33:54 +0200
committerAnthony Liguori <aliguori@us.ibm.com>2009-12-02 08:57:42 -0600
commitd6318738c3ef83b78cf01f44be8c7fff6dba0572 (patch)
tree59856238822092719fc32d34e04d0a08829fff8f /hw/apb_pci.c
parentbe17dc90b51dc76b529615e8c1ab00127da056e0 (diff)
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pci: move apb specific stuff to apb_pci.c
pci code had a TODO to move apb specific pci bridge initialization to apb_pci. Implement this and remove the TODO. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'hw/apb_pci.c')
-rw-r--r--hw/apb_pci.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index f2ed136..fe8faa6 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -182,6 +182,25 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
qemu_set_irq(pic[irq_num], level);
}
+static void apb_pci_bridge_init(PCIBus *b)
+{
+ PCIDevice *dev = pci_bridge_get_device(b);
+
+ /*
+ * command register:
+ * According to PCI bridge spec, after reset
+ * bus master bit is off
+ * memory space enable bit is off
+ * According to manual (805-1251.pdf).
+ * the reset value should be zero unless the boot pin is tied high
+ * (which is true) and thus it should be PCI_COMMAND_MEMORY.
+ */
+ pci_set_word(dev->config + PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ dev->config[PCI_LATENCY_TIMER] = 0x10;
+ dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
+}
+
PCIBus *pci_apb_init(target_phys_addr_t special_base,
target_phys_addr_t mem_base,
qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
@@ -212,10 +231,13 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
pci_apb_map_irq,
"Advanced PCI Bus secondary bridge 1");
+ apb_pci_bridge_init(*bus2);
+
*bus3 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 1),
PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
pci_apb_map_irq,
"Advanced PCI Bus secondary bridge 2");
+ apb_pci_bridge_init(*bus3);
return d->host_state.bus;
}