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| author | Richard Henderson <rth@twiddle.net> | 2016-11-22 16:53:53 +0100 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2016-11-22 16:53:53 +0100 |
| commit | 424ad8388f89f4202a7836d003273f23ebe04b09 (patch) | |
| tree | 8598dcfcb3e07f43b59a5540356a08920eff0585 /hw/alpha | |
| parent | c36ed06e9159fa484b711dfdd27ec64d7ac3d17a (diff) | |
| download | qemu-424ad8388f89f4202a7836d003273f23ebe04b09.zip qemu-424ad8388f89f4202a7836d003273f23ebe04b09.tar.gz qemu-424ad8388f89f4202a7836d003273f23ebe04b09.tar.bz2 | |
target-alpha: Fix interrupt mask for cpu1
A typo prevents ISA interrupts from being recognized on cpu0,
which is where the smp kernel normally wants to see them.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'hw/alpha')
| -rw-r--r-- | hw/alpha/typhoon.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index 883db13..f50f5cf 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -376,7 +376,7 @@ static void cchip_write(void *opaque, hwaddr addr, break; case 0x0240: /* DIM1 */ /* DIM: Device Interrupt Mask Register, CPU1. */ - s->cchip.dim[0] = val; + s->cchip.dim[1] = val; cpu_irq_change(s->cchip.cpu[1], val & s->cchip.drir); break; |