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authorRichard Henderson <richard.henderson@linaro.org>2022-06-10 18:15:34 -0700
committerRichard Henderson <richard.henderson@linaro.org>2022-06-10 18:15:34 -0700
commit30796f556790631c86c733ab06756981be0e1def (patch)
tree3a422366aa9856d1ed62632335610904950b7256 /hw/acpi/viot.c
parent2663c41cfa2c3be34c62de97902a375b81027efd (diff)
parent06cb5c82ebf5fd0f7b3c3de24d650e1259ca6ce4 (diff)
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Merge tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging
virtio,pc,pci: fixes,cleanups,features more CXL patches VIOT Igor's huge AML rework fixes, cleanups all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmKj4YcPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpkNcIAKTsMfUVueTjelC2RwIdegQkypycKhCweKzc # QxddaEr0w+N2164byT3IUy9h53hV3qAAmMuGE4d8B2r5rykf+SwDfIeNmHNqntnA # oLraXIxSSAf4/1cTsRCVL/BXo2E9P+WHI3huw37HClmPLdyMjQa1AtpTpKnIsbmO # sBZf7t5yHDJ2WGZwBQ1IbAxvsdGo1fa1TCt1jZ9g1dmnQSTteQG8DHkGoRnkwTi7 # 510jb0e8uQEgKytCdLTHqESHlfgjvoI73OFOAR2dzTKy6KelFmdLYSo2FtsIdtT5 # 1fZNaDjtl6zQ4b2iLBgPpHtikKch9BzzhDMbCsq7FpvasZ8u2FE= # =LXG0 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 10 Jun 2022 05:27:51 PM PDT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [undefined] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (53 commits) hw/vhost-user-scsi|blk: set `supports_config` flag correctly hw/virtio/vhost-user: don't use uninitialized variable tests/acpi: virt: update golden masters for VIOT hw/acpi/viot: sort VIOT ACPI table entries by PCI host bridge min_bus tests/acpi: virt: allow VIOT acpi table changes hw/acpi/viot: build array of PCI host bridges before generating VIOT ACPI table hw/acpi/viot: move the individual PCI host bridge entry generation to a new function hw/acpi/viot: rename build_pci_range_node() to enumerate_pci_host_bridges() hw/cxl: Fix missing write mask for HDM decoder target list registers pci: fix overflow in snprintf string formatting hw/machine: Drop cxl_supported flag as no longer useful hw/cxl: Move the CXLState from MachineState to machine type specific state. tests/acpi: Update q35/CEDT.cxl for new memory addresses. pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup. tests/acpi: Allow modification of q35 CXL CEDT table. hw/cxl: Push linking of CXL targets into i386/pc rather than in machine.c hw/acpi/cxl: Pass in the CXLState directly rather than MachineState hw/cxl: Make the CXL fixed memory window setup a machine parameter. x86: acpi-build: do not include hw/isa/isa.h directly tests: acpi: update expected DSDT.tis.tpm2/DSDT.tis.tpm12 blobs ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw/acpi/viot.c')
-rw-r--r--hw/acpi/viot.c107
1 files changed, 68 insertions, 39 deletions
diff --git a/hw/acpi/viot.c b/hw/acpi/viot.c
index c1af752..4e0bf69 100644
--- a/hw/acpi/viot.c
+++ b/hw/acpi/viot.c
@@ -10,17 +10,40 @@
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
-struct viot_pci_ranges {
- GArray *blob;
- size_t count;
- uint16_t output_node;
+struct viot_pci_host_range {
+ int min_bus;
+ int max_bus;
};
+static void build_pci_host_range(GArray *table_data, int min_bus, int max_bus,
+ uint16_t output_node)
+{
+ /* Type */
+ build_append_int_noprefix(table_data, 1 /* PCI range */, 1);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 1);
+ /* Length */
+ build_append_int_noprefix(table_data, 24, 2);
+ /* Endpoint start */
+ build_append_int_noprefix(table_data, PCI_BUILD_BDF(min_bus, 0), 4);
+ /* PCI Segment start */
+ build_append_int_noprefix(table_data, 0, 2);
+ /* PCI Segment end */
+ build_append_int_noprefix(table_data, 0, 2);
+ /* PCI BDF start */
+ build_append_int_noprefix(table_data, PCI_BUILD_BDF(min_bus, 0), 2);
+ /* PCI BDF end */
+ build_append_int_noprefix(table_data, PCI_BUILD_BDF(max_bus, 0xff), 2);
+ /* Output node */
+ build_append_int_noprefix(table_data, output_node, 2);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 6);
+}
+
/* Build PCI range for a given PCI host bridge */
-static int build_pci_range_node(Object *obj, void *opaque)
+static int enumerate_pci_host_bridges(Object *obj, void *opaque)
{
- struct viot_pci_ranges *pci_ranges = opaque;
- GArray *blob = pci_ranges->blob;
+ GArray *pci_host_ranges = opaque;
if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
@@ -30,34 +53,31 @@ static int build_pci_range_node(Object *obj, void *opaque)
pci_bus_range(bus, &min_bus, &max_bus);
- /* Type */
- build_append_int_noprefix(blob, 1 /* PCI range */, 1);
- /* Reserved */
- build_append_int_noprefix(blob, 0, 1);
- /* Length */
- build_append_int_noprefix(blob, 24, 2);
- /* Endpoint start */
- build_append_int_noprefix(blob, PCI_BUILD_BDF(min_bus, 0), 4);
- /* PCI Segment start */
- build_append_int_noprefix(blob, 0, 2);
- /* PCI Segment end */
- build_append_int_noprefix(blob, 0, 2);
- /* PCI BDF start */
- build_append_int_noprefix(blob, PCI_BUILD_BDF(min_bus, 0), 2);
- /* PCI BDF end */
- build_append_int_noprefix(blob, PCI_BUILD_BDF(max_bus, 0xff), 2);
- /* Output node */
- build_append_int_noprefix(blob, pci_ranges->output_node, 2);
- /* Reserved */
- build_append_int_noprefix(blob, 0, 6);
-
- pci_ranges->count++;
+ const struct viot_pci_host_range pci_host_range = {
+ .min_bus = min_bus,
+ .max_bus = max_bus,
+ };
+ g_array_append_val(pci_host_ranges, pci_host_range);
}
}
return 0;
}
+static gint pci_host_range_compare(gconstpointer a, gconstpointer b)
+{
+ struct viot_pci_host_range *range_a = (struct viot_pci_host_range *)a;
+ struct viot_pci_host_range *range_b = (struct viot_pci_host_range *)b;
+
+ if (range_a->min_bus < range_b->min_bus) {
+ return -1;
+ } else if (range_a->min_bus > range_b->min_bus) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
/*
* Generate a VIOT table with one PCI-based virtio-iommu that manages PCI
* endpoints.
@@ -72,19 +92,22 @@ void build_viot(MachineState *ms, GArray *table_data, BIOSLinker *linker,
int viommu_off = 48;
AcpiTable table = { .sig = "VIOT", .rev = 0,
.oem_id = oem_id, .oem_table_id = oem_table_id };
- struct viot_pci_ranges pci_ranges = {
- .output_node = viommu_off,
- .blob = g_array_new(false, true /* clear */, 1),
- };
+ GArray *pci_host_ranges = g_array_new(false, true,
+ sizeof(struct viot_pci_host_range));
+ struct viot_pci_host_range *pci_host_range;
+ int i;
/* Build the list of PCI ranges that this viommu manages */
- object_child_foreach_recursive(OBJECT(ms), build_pci_range_node,
- &pci_ranges);
+ object_child_foreach_recursive(OBJECT(ms), enumerate_pci_host_bridges,
+ pci_host_ranges);
+
+ /* Sort the pci host ranges by min_bus */
+ g_array_sort(pci_host_ranges, pci_host_range_compare);
/* ACPI table header */
acpi_table_begin(&table, table_data);
/* Node count */
- build_append_int_noprefix(table_data, pci_ranges.count + 1, 2);
+ build_append_int_noprefix(table_data, pci_host_ranges->len + 1, 2);
/* Node offset */
build_append_int_noprefix(table_data, viommu_off, 2);
/* Reserved */
@@ -105,9 +128,15 @@ void build_viot(MachineState *ms, GArray *table_data, BIOSLinker *linker,
build_append_int_noprefix(table_data, 0, 8);
/* PCI ranges found above */
- g_array_append_vals(table_data, pci_ranges.blob->data,
- pci_ranges.blob->len);
- g_array_free(pci_ranges.blob, true);
+ for (i = 0; i < pci_host_ranges->len; i++) {
+ pci_host_range = &g_array_index(pci_host_ranges,
+ struct viot_pci_host_range, i);
+
+ build_pci_host_range(table_data, pci_host_range->min_bus,
+ pci_host_range->max_bus, viommu_off);
+ }
+
+ g_array_free(pci_host_ranges, true);
acpi_table_end(linker, &table);
}