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| author | Jiajie Chen <c@jia.je> | 2023-08-08 13:42:47 +0800 |
|---|---|---|
| committer | Song Gao <gaosong@loongson.cn> | 2023-08-24 11:17:59 +0800 |
| commit | 17ffe331a923c9015887917b27212ab39ff1d8ea (patch) | |
| tree | 8ae3efa456efe22d4dc5059ff099563f9034e1b0 /gdb-xml/loongarch-fpu.xml | |
| parent | 2948c1fb6b8d806d92394ec358e6ed727e946df9 (diff) | |
| download | qemu-17ffe331a923c9015887917b27212ab39ff1d8ea.zip qemu-17ffe331a923c9015887917b27212ab39ff1d8ea.tar.gz qemu-17ffe331a923c9015887917b27212ab39ff1d8ea.tar.bz2 | |
target/loongarch: Split fcc register to fcc0-7 in gdbstub
Since GDB 13.1(GDB commit ea3352172), GDB LoongArch changed to use
fcc0-7 instead of fcc register. This commit partially reverts commit
2f149c759 (`target/loongarch: Update gdb_set_fpu() and gdb_get_fpu()`)
to match the behavior of GDB.
Note that it is a breaking change for GDB 13.0 or earlier, but it is
also required for GDB 13.1 or later to work.
Signed-off-by: Jiajie Chen <c@jia.je>
Acked-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230808054315.3391465-1-c@jia.je>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Diffstat (limited to 'gdb-xml/loongarch-fpu.xml')
| -rw-r--r-- | gdb-xml/loongarch-fpu.xml | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/gdb-xml/loongarch-fpu.xml b/gdb-xml/loongarch-fpu.xml index 78e42cf..e81e338 100644 --- a/gdb-xml/loongarch-fpu.xml +++ b/gdb-xml/loongarch-fpu.xml @@ -45,6 +45,13 @@ <reg name="f29" bitsize="64" type="fputype" group="float"/> <reg name="f30" bitsize="64" type="fputype" group="float"/> <reg name="f31" bitsize="64" type="fputype" group="float"/> - <reg name="fcc" bitsize="64" type="uint64" group="float"/> + <reg name="fcc0" bitsize="8" type="uint8" group="float"/> + <reg name="fcc1" bitsize="8" type="uint8" group="float"/> + <reg name="fcc2" bitsize="8" type="uint8" group="float"/> + <reg name="fcc3" bitsize="8" type="uint8" group="float"/> + <reg name="fcc4" bitsize="8" type="uint8" group="float"/> + <reg name="fcc5" bitsize="8" type="uint8" group="float"/> + <reg name="fcc6" bitsize="8" type="uint8" group="float"/> + <reg name="fcc7" bitsize="8" type="uint8" group="float"/> <reg name="fcsr" bitsize="32" type="uint32" group="float"/> </feature> |