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| author | Jiajie Chen <c@jia.je> | 2023-08-22 09:13:47 +0200 |
|---|---|---|
| committer | Song Gao <gaosong@loongson.cn> | 2023-08-24 11:17:56 +0800 |
| commit | e70bb6fb9afd0c560b3200b569d9d47239448c30 (patch) | |
| tree | cc15da1ff9d3999a482621cd4c013889f91242c3 /fpu | |
| parent | ebda3036e18b84d3e4280f05ac71ad462593e8ac (diff) | |
| download | qemu-e70bb6fb9afd0c560b3200b569d9d47239448c30.zip qemu-e70bb6fb9afd0c560b3200b569d9d47239448c30.tar.gz qemu-e70bb6fb9afd0c560b3200b569d9d47239448c30.tar.bz2 | |
target/loongarch: Support LoongArch32 TLB entry
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20230822032724.1353391-2-gaosong@loongson.cn>
Message-Id: <20230822071405.35386-2-philmd@linaro.org>
Diffstat (limited to 'fpu')
0 files changed, 0 insertions, 0 deletions