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authorBharata B Rao <bharata@linux.vnet.ibm.com>2017-02-10 12:53:05 +0530
committerDavid Gibson <david@gibson.dropbear.id.au>2017-02-22 11:28:28 +1100
commit9ee6f678f473007e252934d6acd09c24490d9d42 (patch)
treeea047e7fd74f4518830d8bb3a456088dce977fea /fpu
parent5b929608b94fc3ee4104553f961b6b1fae3d7b88 (diff)
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softfloat: Add round-to-odd rounding mode
Power ISA 3.0 introduces a few quadruple precision floating point instructions that support round-to-odd rounding mode. The round-to-odd mode is explained as under: Let Z be the intermediate arithmetic result or the operand of a convert operation. If Z can be represented exactly in the target format, the result is Z. Otherwise the result is either Z1 or Z2 whichever is odd. Here Z1 and Z2 are the next larger and smaller numbers representable in the target format respectively. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'fpu')
-rw-r--r--fpu/softfloat.c21
1 files changed, 20 insertions, 1 deletions
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index c295f31..5ccba76 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -623,6 +623,9 @@ static float64 roundAndPackFloat64(flag zSign, int zExp, uint64_t zSig,
case float_round_down:
roundIncrement = zSign ? 0x3ff : 0;
break;
+ case float_round_to_odd:
+ roundIncrement = (zSig & 0x400) ? 0 : 0x3ff;
+ break;
default:
abort();
}
@@ -632,8 +635,10 @@ static float64 roundAndPackFloat64(flag zSign, int zExp, uint64_t zSig,
|| ( ( zExp == 0x7FD )
&& ( (int64_t) ( zSig + roundIncrement ) < 0 ) )
) {
+ bool overflow_to_inf = roundingMode != float_round_to_odd &&
+ roundIncrement != 0;
float_raise(float_flag_overflow | float_flag_inexact, status);
- return packFloat64( zSign, 0x7FF, - ( roundIncrement == 0 ));
+ return packFloat64(zSign, 0x7FF, -(!overflow_to_inf));
}
if ( zExp < 0 ) {
if (status->flush_to_zero) {
@@ -651,6 +656,13 @@ static float64 roundAndPackFloat64(flag zSign, int zExp, uint64_t zSig,
if (isTiny && roundBits) {
float_raise(float_flag_underflow, status);
}
+ if (roundingMode == float_round_to_odd) {
+ /*
+ * For round-to-odd case, the roundIncrement depends on
+ * zSig which just changed.
+ */
+ roundIncrement = (zSig & 0x400) ? 0 : 0x3ff;
+ }
}
}
if (roundBits) {
@@ -1149,6 +1161,9 @@ static float128 roundAndPackFloat128(flag zSign, int32_t zExp,
case float_round_down:
increment = zSign && zSig2;
break;
+ case float_round_to_odd:
+ increment = !(zSig1 & 0x1) && zSig2;
+ break;
default:
abort();
}
@@ -1168,6 +1183,7 @@ static float128 roundAndPackFloat128(flag zSign, int32_t zExp,
if ( ( roundingMode == float_round_to_zero )
|| ( zSign && ( roundingMode == float_round_up ) )
|| ( ! zSign && ( roundingMode == float_round_down ) )
+ || (roundingMode == float_round_to_odd)
) {
return
packFloat128(
@@ -1215,6 +1231,9 @@ static float128 roundAndPackFloat128(flag zSign, int32_t zExp,
case float_round_down:
increment = zSign && zSig2;
break;
+ case float_round_to_odd:
+ increment = !(zSig1 & 0x1) && zSig2;
+ break;
default:
abort();
}