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| author | Sean Christopherson <sean.j.christopherson@intel.com> | 2021-07-19 19:21:20 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2021-09-30 15:30:24 +0200 |
| commit | 0cf4ce00d2255ef48d560d36559e7a4cda41748b (patch) | |
| tree | 2cde7cc6171a27ec4cc2f77c9d1e51685fc2f434 /fpu | |
| parent | e2560114cdb127985b75ec2554cb2f0d91dd03f3 (diff) | |
| download | qemu-0cf4ce00d2255ef48d560d36559e7a4cda41748b.zip qemu-0cf4ce00d2255ef48d560d36559e7a4cda41748b.tar.gz qemu-0cf4ce00d2255ef48d560d36559e7a4cda41748b.tar.bz2 | |
hw/i386/pc: Account for SGX EPC sections when calculating device memory
Add helpers to detect if SGX EPC exists above 4g, and if so, where SGX
EPC above 4g ends. Use the helpers to adjust the device memory range
if SGX EPC exists above 4g.
For multiple virtual EPC sections, we just put them together physically
contiguous for the simplicity because we don't support EPC NUMA affinity
now. Once the SGX EPC NUMA support in the kernel SGX driver, we will
support this in the future.
Note that SGX EPC is currently hardcoded to reside above 4g.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-18-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'fpu')
0 files changed, 0 insertions, 0 deletions