diff options
| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2023-03-02 13:37:03 +0000 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2023-03-07 12:39:00 -0500 |
| commit | 9a6ef182c03eaa138bae553f0fbb5a123bef9a53 (patch) | |
| tree | 6630f3d020883248caa4293c3bda0c8c31e0d51d /event-loop-base.c | |
| parent | 010746ae1db7f52700cb2e2c46eb94f299cfa0d2 (diff) | |
| download | qemu-9a6ef182c03eaa138bae553f0fbb5a123bef9a53.zip qemu-9a6ef182c03eaa138bae553f0fbb5a123bef9a53.tar.gz qemu-9a6ef182c03eaa138bae553f0fbb5a123bef9a53.tar.bz2 | |
hw/pci/aer: Add missing routing for AER errors
PCIe r6.0 Figure 6-3 "Pseudo Logic Diagram for Selected Error Message Control
and Status Bits" includes a right hand branch under "All PCI Express devices"
that allows for messages to be generated or sent onwards without SERR#
being set as long as the appropriate per error class bit in the PCIe
Device Control Register is set.
Implement that branch thus enabling routing of ERR_COR, ERR_NONFATAL
and ERR_FATAL under OSes that set these bits appropriately (e.g. Linux)
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Message-Id: <20230302133709.30373-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Diffstat (limited to 'event-loop-base.c')
0 files changed, 0 insertions, 0 deletions