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| author | Peter Maydell <peter.maydell@linaro.org> | 2023-09-15 19:54:53 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-10-27 11:41:13 +0100 |
| commit | dfff1000fef24f6686e0be5e6472613985a363dc (patch) | |
| tree | 9fd94af197b25523fb6d52db395f3c669840a2b1 /docs | |
| parent | 3bcc53980b05dbcdc9bc70fc7ec3bc37320edcbd (diff) | |
| download | qemu-dfff1000fef24f6686e0be5e6472613985a363dc.zip qemu-dfff1000fef24f6686e0be5e6472613985a363dc.tar.gz qemu-dfff1000fef24f6686e0be5e6472613985a363dc.tar.bz2 | |
target/arm: Implement Neoverse N2 CPU model
Implement a model of the Neoverse N2 CPU. This is an Armv9.0-A
processor very similar to the Cortex-A710. The differences are:
* no FEAT_EVT
* FEAT_DGH (data gathering hint)
* FEAT_NV (not yet implemented in QEMU)
* Statistical Profiling Extension (not implemented in QEMU)
* 48 bit physical address range, not 40
* CTR_EL0.DIC = 1 (no explicit icache cleaning needed)
* PMCR_EL0.N = 6 (always 6 PMU counters, not 20)
Because it has 48-bit physical address support, we can use
this CPU in the sbsa-ref board as well as the virt board.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20230915185453.1871167-3-peter.maydell@linaro.org
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/system/arm/virt.rst | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index e1697ac..7c4c801 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -63,6 +63,7 @@ Supported guest CPU types: - ``host`` (with KVM only) - ``neoverse-n1`` (64-bit) - ``neoverse-v1`` (64-bit) +- ``neoverse-n2`` (64-bit) - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) Note that the default is ``cortex-a15``, so for an AArch64 guest you must |