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| author | Peter Maydell <peter.maydell@linaro.org> | 2023-02-02 10:10:07 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-02-02 10:10:07 +0000 |
| commit | deabea6e88f7c4c3c12a36ee30051c6209561165 (patch) | |
| tree | f32d252f632936ba594c74f77100188e2b0309f6 /docs | |
| parent | 026817fb69414c9d3909d8b1a209f90180d777d6 (diff) | |
| parent | f5cb612867d3b10b86d6361ba041767e02c1b127 (diff) | |
| download | qemu-deabea6e88f7c4c3c12a36ee30051c6209561165.zip qemu-deabea6e88f7c4c3c12a36ee30051c6209561165.tar.gz qemu-deabea6e88f7c4c3c12a36ee30051c6209561165.tar.bz2 | |
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging
virtio,pc,pci: features, cleanups, fixes
lots of fixes, cleanups
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# -----BEGIN PGP SIGNATURE-----
#
# iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmPYJdcPHG1zdEByZWRo
# YXQuY29tAAoJECgfDbjSjVRp08cIAMYq0y++RtepDpLnPjybR0v1G4cPgZS4DXFz
# 8uc/2nkAHe1Q2lJNmk9p3YjLLloSO8yC1bmuuhUpmry9BJokYzY1r7rfXc8jd/Za
# z2FjC9LuYX+sk26NTGUxPq9mhT0p14HXyoxpnQlCweuVL0DJg1Tip6HI4oOG2LJj
# Au6Rl9keMQNqf9qVtsR1djO+8nO4ywbx6D9d2CYSKkQ3pK3uLvNds9vqU16x8wq7
# mNPqV8BIoDgW4zEOL478h6rJcL7pDQo6kAT1wfg7q1JcMMHJfW36VcBeFfskfJFg
# Pej3TEP2rg1LsGfh5XVw5Rp6FZ4K2TEyTK9cPZ9F7CzKdUrgBHU=
# =S0zd
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 30 Jan 2023 20:17:27 GMT
# gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (56 commits)
docs/pcie.txt: Replace ioh3420 with pcie-root-port
Revert "vhost-user: Introduce nested event loop in vhost_user_read()"
Revert "vhost-user: Monitor slave channel in vhost_user_read()"
tests/qtest/bios-tables-test: Make the test less verbose by default
hw: Use TYPE_PCI_BUS definition where appropriate
vhost-user: Skip unnecessary duplicated VHOST_USER_ADD/REM_MEM_REG requests
tests: acpi: update expected blobs
pcihp: generate populated non-hotpluggble slot descriptions on non-hotplug path
tests: acpi: whitelist DSDT before moving non-hotpluggble slots description from hotplug path
tests: acpi: update expected blobs
pcihp: acpi: ignore coldplugged bridges when composing hotpluggable slots
tests: acpi: whitelist DSDT blobs before removing dynamic _DSM on coldplugged bridges
tests: acpi: update expected blobs
pcihp: acpi: decouple hotplug and generic slots description
tests: acpi: whitelist DSDT before decoupling PCI hotplug code from basic slots description
pcihp: isolate rule whether slot should be described in DSDT
pci: make sure pci_bus_is_express() won't error out with "discards ‘const’ qualifier"
pcihp: make bridge describe itself using AcpiDevAmlIfClass:build_dev_aml
pci: acpi: wire up AcpiDevAmlIf interface to generic bridge
x86: pcihp: acpi: prepare slot ignore rule to work with self describing bridges
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/pcie.txt | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/docs/pcie.txt b/docs/pcie.txt index 89e3502..df49178 100644 --- a/docs/pcie.txt +++ b/docs/pcie.txt @@ -48,8 +48,8 @@ Place only the following kinds of devices directly on the Root Complex: strangely when PCI Express devices are integrated with the Root Complex. - (2) PCI Express Root Ports (ioh3420), for starting exclusively PCI Express - hierarchies. + (2) PCI Express Root Ports (pcie-root-port), for starting exclusively + PCI Express hierarchies. (3) PCI Express to PCI Bridge (pcie-pci-bridge), for starting legacy PCI hierarchies. @@ -70,7 +70,7 @@ Place only the following kinds of devices directly on the Root Complex: -device pxb-pcie,id=pcie.1,bus_nr=x[,numa_node=y][,addr=z] PCI Express Root Ports and PCI Express to PCI bridges can be connected to the pcie.1 bus: - -device ioh3420,id=root_port1[,bus=pcie.1][,chassis=x][,slot=y][,addr=z] \ + -device pcie-root-port,id=root_port1[,bus=pcie.1][,chassis=x][,slot=y][,addr=z] \ -device pcie-pci-bridge,id=pcie_pci_bridge1,bus=pcie.1 @@ -112,14 +112,14 @@ Plug only PCI Express devices into PCI Express Ports. ------------ 2.2.1 Plugging a PCI Express device into a PCI Express Root Port: - -device ioh3420,id=root_port1,chassis=x,slot=y[,bus=pcie.0][,addr=z] \ + -device pcie-root-port,id=root_port1,chassis=x,slot=y[,bus=pcie.0][,addr=z] \ -device <dev>,bus=root_port1 2.2.2 Using multi-function PCI Express Root Ports: - -device ioh3420,id=root_port1,multifunction=on,chassis=x,addr=z.0[,slot=y][,bus=pcie.0] \ - -device ioh3420,id=root_port2,chassis=x1,addr=z.1[,slot=y1][,bus=pcie.0] \ - -device ioh3420,id=root_port3,chassis=x2,addr=z.2[,slot=y2][,bus=pcie.0] \ + -device pcie-root-port,id=root_port1,multifunction=on,chassis=x,addr=z.0[,slot=y][,bus=pcie.0] \ + -device pcie-root-port,id=root_port2,chassis=x1,addr=z.1[,slot=y1][,bus=pcie.0] \ + -device pcie-root-port,id=root_port3,chassis=x2,addr=z.2[,slot=y2][,bus=pcie.0] \ 2.2.3 Plugging a PCI Express device into a Switch: - -device ioh3420,id=root_port1,chassis=x,slot=y[,bus=pcie.0][,addr=z] \ + -device pcie-root-port,id=root_port1,chassis=x,slot=y[,bus=pcie.0][,addr=z] \ -device x3130-upstream,id=upstream_port1,bus=root_port1[,addr=x] \ -device xio3130-downstream,id=downstream_port1,bus=upstream_port1,chassis=x1,slot=y1[,addr=z1]] \ -device <dev>,bus=downstream_port1 |