Merge tag 'pull-riscv-to-apply-20220610' of github.com:alistair23/qemu into staging

Fourth RISC-V PR for QEMU 7.1

* Update MAINTAINERS
* Add support for Zmmul extension
* Fixup FDT errors when supplying device tree from the command line for virt machine
* Avoid overflowing the addr_config buffer in the SiFive PLIC
* Support -device loader addresses above 2GB
* Correctly wake from WFI on VS-level external interrupts
* Fixes for RV128 support
* Support Vector extension tail agnostic setting elements' bits to all 1s
* Don't expose the CPU properties on named CPUs
* Fix vector extension assert for RV32

# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmKix74ACgkQIeENKd+X
# cFTKdgf8DP85Mf91+m1Dd1zji6d4JiFa+i7wer5T6la7qQAiIbyyq6kax0K31YYF
# QuX3x7i9erF8Z/kox3MlYjjytPS0iJK9+Fica1ttslBJLv/o2K7SAaLmUwS65AB5
# rHjRCWDdeA3zPv7tcHEIpYZNFb163N2ZYqhmTTmL6Q0KTaa73OWKuJIbJzB8iT85
# LH1cUTfCEWNzsG0PLAD4Xh4ug4Hq6sW54NXXMDZiDSVak/FdNSEzuUMUsNW12XA1
# ib1uhfygHGYfSXFUgYmCiHK7iEey7A9IZtGKdNIXObx1/QVOrvyW+E90XRQqEHHC
# XeOkdTUB2YfPsC0Qs4VVqsVEQVjUCw==
# =gz3H
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 09 Jun 2022 09:25:34 PM PDT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20220610' of github.com:alistair23/qemu: (25 commits)
  target/riscv: trans_rvv: Avoid assert for RV32 and e64
  target/riscv: Don't expose the CPU properties on names CPUs
  target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior
  target/riscv: rvv: Add tail agnostic for vector permutation instructions
  target/riscv: rvv: Add tail agnostic for vector mask instructions
  target/riscv: rvv: Add tail agnostic for vector reduction instructions
  target/riscv: rvv: Add tail agnostic for vector floating-point instructions
  target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
  target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
  target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
  target/riscv: rvv: Add tail agnostic for vector integer shift instructions
  target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
  target/riscv: rvv: Add tail agnostic for vector load / store instructions
  target/riscv: rvv: Add tail agnostic for vv instructions
  target/riscv: rvv: Early exit when vstart >= vl
  target/riscv: rvv: Rename ambiguous esz
  target/riscv: rvv: Prune redundant access_type parameter passed
  target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
  target/riscv/debug.c: keep experimental rv128 support working
  target/riscv: Wake on VS-level external interrupts
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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