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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-06-22 16:30:46 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-06-23 11:21:43 +0100 |
| commit | 57223a4c24d58493d1eade8c1b38fd707f845d5e (patch) | |
| tree | 77ea8ce7871c6d57736f29cc7bc7b397f5f001f4 /docs | |
| parent | a834d5474e24a279ffc16558c34d4536e84fe09d (diff) | |
| download | qemu-57223a4c24d58493d1eade8c1b38fd707f845d5e.zip qemu-57223a4c24d58493d1eade8c1b38fd707f845d5e.tar.gz qemu-57223a4c24d58493d1eade8c1b38fd707f845d5e.tar.bz2 | |
docs/system/arm: Document FEAT_RME
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20230622143046.1578160-1-richard.henderson@linaro.org
[PMM: fixed typo; note experimental status in emulation.rst too]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/system/arm/cpu-features.rst | 23 | ||||
| -rw-r--r-- | docs/system/arm/emulation.rst | 1 |
2 files changed, 24 insertions, 0 deletions
diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst index f4524b6..6bb88a4 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -435,3 +435,26 @@ As with ``sve-default-vector-length``, if the default length is larger than the maximum vector length enabled, the actual vector length will be reduced. If this property is set to ``-1`` then the default vector length is set to the maximum possible length. + +RME CPU Properties +================== + +The status of RME support with QEMU is experimental. At this time we +only support RME within the CPU proper, not within the SMMU or GIC. +The feature is enabled by the CPU property ``x-rme``, with the ``x-`` +prefix present as a reminder of the experimental status, and defaults off. + +The method for enabling RME will change in some future QEMU release +without notice or backward compatibility. + +RME Level 0 GPT Size Property +----------------------------- + +To aid firmware developers in testing different possible CPU +configurations, ``x-l0gptsz=S`` may be used to specify the value +to encode into ``GPCCR_EL3.L0GPTSZ``, a read-only field that +specifies the size of the Level 0 Granule Protection Table. +Legal values for ``S`` are 30, 34, 36, and 39; the default is 30. + +As with ``x-rme``, the ``x-l0gptsz`` property may be renamed or +removed in some future QEMU release. diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index ecbbd63..bdafc68 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -66,6 +66,7 @@ the following architecture extensions: - FEAT_RAS (Reliability, availability, and serviceability) - FEAT_RASv1p1 (RAS Extension v1.1) - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) +- FEAT_RME (Realm Management Extension) (NB: support status in QEMU is experimental) - FEAT_RNG (Random number generator) - FEAT_S2FWB (Stage 2 forced Write-Back) - FEAT_SB (Speculation Barrier) |