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author | Peter Maydell <peter.maydell@linaro.org> | 2020-03-17 11:05:08 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2020-03-17 11:05:08 +0000 |
commit | 3189e9d38c82266ea5750a81255fd229c7ddf1e6 (patch) | |
tree | 081053039d7613158c1214c406369afe4a336c35 /docs | |
parent | a98135f727595382e200d04c2996e868b7925a01 (diff) | |
parent | c5969a3a3c2cb9ea02ffb7e86acb059d3cf8c264 (diff) | |
download | qemu-3189e9d38c82266ea5750a81255fd229c7ddf1e6.zip qemu-3189e9d38c82266ea5750a81255fd229c7ddf1e6.tar.gz qemu-3189e9d38c82266ea5750a81255fd229c7ddf1e6.tar.bz2 |
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf5' into staging
RISC-V Patches for the 5.0 Soft Freeze, Part 5
This tag contains the last of the patches I'd like to target for the 5.0 soft
freeze. At this point we're mostly collecting fixes, but there are a few new
features. The changes include:
* An OpenSBI update, including the various bits necessary to put CI together
and an image for the 32-bit sifive_u board.
* A fix that disallows TSR when outside of machine mode.
* A fix for VS-mode interrupt forwarding.
# gpg: Signature made Tue 17 Mar 2020 03:59:58 GMT
# gpg: using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889
# gpg: issuer "palmer@dabbelt.com"
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown]
# gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown]
# gpg: aka "Palmer Dabbelt <palmerdabbelt@google.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41
# Subkey fingerprint: 2B3C 3747 4468 43B2 4A94 3A7A 2E13 19F3 5FBB 1889
* remotes/palmer/tags/riscv-for-master-5.0-sf5:
target/riscv: Fix VS mode interrupts forwarding.
gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries
riscv: sifive_u: Update BIOS_FILENAME for 32-bit
roms: opensbi: Add 32-bit firmware image for sifive_u machine
roms: opensbi: Upgrade from v0.5 to v0.6
target/riscv: Correctly implement TSR trap
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'docs')
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