diff options
| author | Stefan Hajnoczi <stefanha@redhat.com> | 2025-03-28 08:06:53 -0400 |
|---|---|---|
| committer | Stefan Hajnoczi <stefanha@redhat.com> | 2025-03-28 08:06:53 -0400 |
| commit | 0f15892acaf3f50ecc20c6dad4b3ebdd701aa93e (patch) | |
| tree | 706da44aabb6af77878877d985ce4cb600ac91ef /docs | |
| parent | 911a444ba63e4471917595860cff66d05008ce12 (diff) | |
| parent | 897c68fb795cf03b89b6688a6f945d68a765c3e4 (diff) | |
| download | qemu-0f15892acaf3f50ecc20c6dad4b3ebdd701aa93e.zip qemu-0f15892acaf3f50ecc20c6dad4b3ebdd701aa93e.tar.gz qemu-0f15892acaf3f50ecc20c6dad4b3ebdd701aa93e.tar.bz2 | |
Merge tag 'pull-riscv-to-apply-20250328' of https://github.com/alistair23/qemu into staging
Fifth RISC-V PR for 10.0
* Add docs/specs/riscv-iommu.rst to MAINTAINERS
* Fix broken link to external risv iommu document
* Revert scounteren and senvcfg to fixup older kernel boots
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmfmR0UACgkQr3yVEwxT
# gBOdqw/9GeSsIO4DDQ9Zu6C+v4pj9SXuvdpJrO0JBKXdrhp3OH9kVVR5nGvGA1pt
# S155AhH8D/pjpMM1exYfBylqTB+CiwjCZnvakvlxx8FkBuDQ/xPBEoPz00TAFAli
# 93TDys83HJWk0UDXCCr8Ch7VhaEX07IyFNFz9TQiNNm0zsK4DRtfmYgGQ+RbkIny
# 9PxZf6Dz1vfASXGu66EMA1CFaFzXXpxQZtx39OKwfJ4tRj8J/jUFvUtPnP4/sOxH
# lyGKIgOfBaSW2AenCoYjPGlRbbdET2YG+IMiqvo5Ie94lZASA6g/8p6zZaBH0RIC
# eUNJM7QjimZAIhzhS9xr/Jz/JGY/aeHgVcyPzWVMSty1Qa3a1hsuD/2UFxXadelL
# 2QGcVRn2o/3GqgjL+8s7A4c79vjQ8kRSI2GqSaUJ5PGdq/xHC6+f08VfqoZZRWEE
# YtzaPh96f6MZT0UdIqCLAG7UfUpYySabzMyYSop7Wqy+O4/bMK2LFtA4IDpomdha
# +ZSvCYYarvBDWaTYcbeX2hRnRoF0H5HVK3GYgt088mp4qL+6hM5oxMS2AK/iMuEi
# rW2TVk8CfwvGGgLXVj/fmMJ6P6XaIPvo0mvJ2Er67aQFXN+o2IzDqtIH9VUjJFhr
# EKiPq0RpX2BBeoi6vtU1Qf2kUj3GHPENACvErC8BlgyywXReb74=
# =Xno2
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 28 Mar 2025 02:52:53 EDT
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20250328' of https://github.com/alistair23/qemu:
Revert "target/riscv/kvm: add missing KVM CSRs"
docs/specs/riscv-iommu: Fixed broken link to external risv iommu document
docs: Added docs/specs/riscv-iommu.rst in MAINTAINERS file.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/specs/riscv-iommu.rst | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/docs/specs/riscv-iommu.rst b/docs/specs/riscv-iommu.rst index 000c7e1..991d376 100644 --- a/docs/specs/riscv-iommu.rst +++ b/docs/specs/riscv-iommu.rst @@ -4,7 +4,7 @@ RISC-V IOMMU support for RISC-V machines ======================================== QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec -version 1.0 `iommu1.0`_. +version 1.0 `iommu1.0.0`_. The emulation includes a PCI reference device (riscv-iommu-pci) and a platform bus device (riscv-iommu-sys) that QEMU RISC-V boards can use. The 'virt' @@ -14,7 +14,7 @@ riscv-iommu-pci reference device -------------------------------- This device implements the RISC-V IOMMU emulation as recommended by the section -"Integrating an IOMMU as a PCIe device" of `iommu1.0`_: a PCI device with base +"Integrating an IOMMU as a PCIe device" of `iommu1.0.0`_: a PCI device with base class 08h, sub-class 06h and programming interface 00h. As a reference device it doesn't implement anything outside of the specification, @@ -109,7 +109,7 @@ riscv-iommu options: - "s-stage": enabled - "g-stage": enabled -.. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf +.. _iommu1.0.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0.0/riscv-iommu.pdf .. _linux-v8: https://lore.kernel.org/linux-riscv/cover.1718388908.git.tjeznach@rivosinc.com/ |