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authorPeter Maydell <peter.maydell@linaro.org>2024-09-03 17:22:16 +0100
committerPeter Maydell <peter.maydell@linaro.org>2024-09-05 13:12:36 +0100
commit5d1187b308e4a55285b744567e3c7078689a3b2e (patch)
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parent0e1850182a1faae23fcafc069a0af929930b20bb (diff)
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target/arm: Enable FEAT_EBF16 in the "max" CPU
Now that we've implemented the required behaviour for FEAT_EBF16, we can enable it for the "max" CPU type, list it in our documentation, and delete a TODO comment about it being missing. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'docs/system/arm')
-rw-r--r--docs/system/arm/emulation.rst1
1 files changed, 1 insertions, 0 deletions
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 3ab6e72..35f52a5 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -45,6 +45,7 @@ the following architecture extensions:
- FEAT_DotProd (Advanced SIMD dot product instructions)
- FEAT_DoubleFault (Double Fault Extension)
- FEAT_E0PD (Preventing EL0 access to halves of address maps)
+- FEAT_EBF16 (AArch64 Extended BFloat16 instructions)
- FEAT_ECV (Enhanced Counter Virtualization)
- FEAT_EL0 (Support for execution at EL0)
- FEAT_EL1 (Support for execution at EL1)