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| author | hemanshu.khilari.foss <hemanshu.khilari.foss@gmail.com> | 2025-03-23 12:04:00 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-03-28 16:49:57 +1000 |
| commit | e768f0246ce2625880800a2bdce78438b5e9282c (patch) | |
| tree | 6d8e42be075483d257d07d7b03195926a98ff527 /docs/specs | |
| parent | 4a7b8c3f5c7ecf673eabdd8505c7738bda40f813 (diff) | |
| download | qemu-e768f0246ce2625880800a2bdce78438b5e9282c.zip qemu-e768f0246ce2625880800a2bdce78438b5e9282c.tar.gz qemu-e768f0246ce2625880800a2bdce78438b5e9282c.tar.bz2 | |
docs/specs/riscv-iommu: Fixed broken link to external risv iommu document
The links to riscv iommu specification document are incorrect. This patch
updates all the said link to point to correct location.
Cc: qemu-stable@nongnu.org
Cc: qemu-riscv@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2808
Signed-off-by: hemanshu.khilari.foss <hemanshu.khilari.foss@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250323063404.13206-1-hemanshu.khilari.foss@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'docs/specs')
| -rw-r--r-- | docs/specs/riscv-iommu.rst | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/docs/specs/riscv-iommu.rst b/docs/specs/riscv-iommu.rst index 000c7e1..991d376 100644 --- a/docs/specs/riscv-iommu.rst +++ b/docs/specs/riscv-iommu.rst @@ -4,7 +4,7 @@ RISC-V IOMMU support for RISC-V machines ======================================== QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec -version 1.0 `iommu1.0`_. +version 1.0 `iommu1.0.0`_. The emulation includes a PCI reference device (riscv-iommu-pci) and a platform bus device (riscv-iommu-sys) that QEMU RISC-V boards can use. The 'virt' @@ -14,7 +14,7 @@ riscv-iommu-pci reference device -------------------------------- This device implements the RISC-V IOMMU emulation as recommended by the section -"Integrating an IOMMU as a PCIe device" of `iommu1.0`_: a PCI device with base +"Integrating an IOMMU as a PCIe device" of `iommu1.0.0`_: a PCI device with base class 08h, sub-class 06h and programming interface 00h. As a reference device it doesn't implement anything outside of the specification, @@ -109,7 +109,7 @@ riscv-iommu options: - "s-stage": enabled - "g-stage": enabled -.. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf +.. _iommu1.0.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0.0/riscv-iommu.pdf .. _linux-v8: https://lore.kernel.org/linux-riscv/cover.1718388908.git.tjeznach@rivosinc.com/ |