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| author | Max Filippov <jcmvbkbc@gmail.com> | 2015-06-29 10:50:03 +0300 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2015-07-06 13:25:11 +0300 |
| commit | ddd44279fdbc545a9182cb642645af8a4672c267 (patch) | |
| tree | 2419cab26d887b77965daef5fdf552356523c589 /docs/specs | |
| parent | f50a1640fb82708a5d528dee1ace42a224b95b15 (diff) | |
| download | qemu-ddd44279fdbc545a9182cb642645af8a4672c267.zip qemu-ddd44279fdbc545a9182cb642645af8a4672c267.tar.gz qemu-ddd44279fdbc545a9182cb642645af8a4672c267.tar.bz2 | |
target-xtensa: add 64-bit floating point registers
Xtensa ISA got specification for 64-bit floating point registers and
opcodes, see ISA, 4.3.11 "Floating point coprocessor option".
Add 64-bit FP registers.
Although 64-bit floating point is currently not supported by xtensa
translator, these registers need to be reported to gdb with proper size,
otherwise it wouldn't find other registers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'docs/specs')
0 files changed, 0 insertions, 0 deletions