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authorEric Auger <eric.auger@redhat.com>2025-02-18 19:25:35 +0100
committerMichael S. Tsirkin <mst@redhat.com>2025-02-21 07:21:25 -0500
commitdd6d545e8f2d9a0e8a8c287ec16469f03ef5c198 (patch)
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docs/devel/reset: Document reset expectations for DMA and IOMMU
To avoid any translation faults, the IOMMUs are expected to be reset after the devices they protect. Document that we expect DMA requests to be stopped during the 'enter' or 'hold' phase while IOMMUs should be reset during the 'exit' phase. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Message-Id: <20250218182737.76722-6-eric.auger@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'docs/devel')
-rw-r--r--docs/devel/reset.rst5
1 files changed, 5 insertions, 0 deletions
diff --git a/docs/devel/reset.rst b/docs/devel/reset.rst
index adefd59..0b8b2fa 100644
--- a/docs/devel/reset.rst
+++ b/docs/devel/reset.rst
@@ -143,6 +143,11 @@ The *exit* phase is executed only when the last reset operation ends. Therefore
the object does not need to care how many of reset controllers it has and how
many of them have started a reset.
+DMA capable devices are expected to cancel all outstanding DMA operations
+during either 'enter' or 'hold' phases. IOMMUs are expected to reset during
+the 'exit' phase and this sequencing makes sure no outstanding DMA request
+will fault.
+
Handling reset in a resettable object
-------------------------------------