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author | Jim Wilson <jimw@sifive.com> | 2019-03-15 03:26:59 -0700 |
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committer | Palmer Dabbelt <palmer@sifive.com> | 2019-03-19 05:13:24 -0700 |
commit | 5371f5cd7170f29310575977f89e6e35d4d65168 (patch) | |
tree | a280c7f86b3384f0590559191800771a898c8400 /crypto | |
parent | 753e3fe207db08ce0ef0405e8452c3397c9b9308 (diff) | |
download | qemu-5371f5cd7170f29310575977f89e6e35d4d65168.zip qemu-5371f5cd7170f29310575977f89e6e35d4d65168.tar.gz qemu-5371f5cd7170f29310575977f89e6e35d4d65168.tar.bz2 |
RISC-V: Add hooks to use the gdb xml files.
The gdb CSR xml file has registers in documentation order, not numerical
order, so we need a table to map the register numbers. This also adds
fairly standard gdb hooks to access xml specified registers.
notice:
The fpu xml from gdb 8.3 has unused register #, 65 and make first
csr register # become 69. We register extra register on gdb to correct
csr offset calculation
Signed-off-by: Jim Wilson <jimw@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'crypto')
0 files changed, 0 insertions, 0 deletions