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| author | Yongbok Kim <yongbok.kim@imgtec.com> | 2015-06-25 00:24:18 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2015-06-26 09:22:05 +0100 |
| commit | e29c962804c4dd3fabd44e703aa87eec555ed910 (patch) | |
| tree | ec1c39ea7838439a678e688ae478b707ca2e9a9a /cpu-exec.c | |
| parent | 6893f07466b045c5faf314ab9e57ef3b4a6f9e49 (diff) | |
| download | qemu-e29c962804c4dd3fabd44e703aa87eec555ed910.zip qemu-e29c962804c4dd3fabd44e703aa87eec555ed910.tar.gz qemu-e29c962804c4dd3fabd44e703aa87eec555ed910.tar.bz2 | |
target-mips: raise RI exceptions when FIR.PS = 0
64-bit paired-single (PS) floating point data type is optional in the
pre-Release 6.
It has to raise RI exception when PS type is not implemented. (FIR.PS = 0)
(The PS data type is removed in the Release 6.)
Loongson-2E and Loongson-2F don't have any implementation field in
FCSR0(FIR) but do support PS data format, therefore for these cores RI will
not be signalled regardless of PS bit.
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'cpu-exec.c')
0 files changed, 0 insertions, 0 deletions