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authorFabiano Rosas <farosas@linux.ibm.com>2021-06-01 18:46:47 -0300
committerDavid Gibson <david@gibson.dropbear.id.au>2021-06-03 18:10:31 +1000
commit51b385db586dafa4cd1f23413f0cbbf5ec2a256c (patch)
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parent0c87018c7c171a8fe0ed44b9aa931b364eec85f7 (diff)
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target/ppc: powerpc_excp: Consolidade TLB miss code
The only difference in the code for Instruction fetch, Data load and Data store TLB miss errors is that when called from an unsupported processor (i.e. not one of 602, 603, 603e, G2, 7x5 or 74xx), they abort with a message specific to the operation type (insn fetch, data load/store). If a processor does not support those interrupts we should not be registering them in init_excp_<proc> to begin with, so that error message would never be used. I'm leaving the message in for completeness, but making it generic and consolidating the three interrupts into the same case statement body. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20210601214649.785647-4-farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'chardev/testdev.c')
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