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| author | Warner Losh <imp@bsdimp.com> | 2024-09-17 01:51:14 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-10-02 15:11:52 +1000 |
| commit | 25b08c4da891648be6a3230e580250ef8015486d (patch) | |
| tree | d57100a1d8f62ae008a1bbdcfffc3d7e14f4d433 /bsd-user | |
| parent | 9cc1a9cd4fe3f1f5307fb470ee11745566bbd857 (diff) | |
| download | qemu-25b08c4da891648be6a3230e580250ef8015486d.zip qemu-25b08c4da891648be6a3230e580250ef8015486d.tar.gz qemu-25b08c4da891648be6a3230e580250ef8015486d.tar.bz2 | |
bsd-user: Add generic RISC-V64 target definitions
Added a generic definition for RISC-V64 target-specific details.
Implemented the 'regpairs_aligned' function,which returns 'false'
to indicate that register pairs are not aligned in the RISC-V64 ABI.
Signed-off-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240916155119.14610-13-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'bsd-user')
| -rw-r--r-- | bsd-user/riscv/target.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/bsd-user/riscv/target.h b/bsd-user/riscv/target.h new file mode 100644 index 0000000..036ddd1 --- /dev/null +++ b/bsd-user/riscv/target.h @@ -0,0 +1,20 @@ +/* + * Riscv64 general target stuff that's common to all aarch details + * + * Copyright (c) 2022 M. Warner Losh <imp@bsdimp.com> + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef TARGET_H +#define TARGET_H + +/* + * riscv64 ABI does not 'lump' the registers for 64-bit args. + */ +static inline bool regpairs_aligned(void *cpu_env) +{ + return false; +} + +#endif /* TARGET_H */ |